Fingerprint Sensor Interlayer Dielectric Segmentation
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Solution Overview
Problem
Existing fingerprint sensor devices have limitations in sensitivity and fabrication costs, with challenges in achieving optimal performance and miniaturization due to the constraints of via width and interlayer dielectric thickness in semiconductor devices.
Innovation Solution
The semiconductor device design includes a semiconductor substrate with a first and second via formed in separate processes within an interlayer dielectric layer, allowing for increased thickness without expanding via widths, enabling better sensitivity and miniaturization in fingerprint sensor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the interlayer dielectric thickness is increased to improve sensitivity, then the sensitivity is improved, but the via width must be increased which increases device area
Solution Approach 1:
The interlayer dielectric layer is segmented into multiple sections with different thicknesses. A first via connects to a first region with a first thickness, while a second via connects to a second region with a second thickness greater than the first thickness. This segmentation allows optimization of sensitivity for specific via locations without uniformly increasing the entire interlayer dielectric thickness, thereby maintaining compact device area.
Solution Approach 2:
Different regions of the interlayer dielectric layer are assigned different thicknesses based on local requirements. The region under the second via has greater thickness to enhance sensitivity for that specific connection, while other regions maintain smaller thickness to minimize overall device area. This local quality approach ensures sensitivity enhancement is applied only where needed.
2Measurement precision
If the interlayer dielectric thickness is increased to improve sensitivity, then the sensitivity is improved, but the fabrication complexity increases
Solution Approach 1:
The interlayer dielectric layer is formed in multiple stages with different thicknesses using sequential deposition or selective growth processes. This segmentation is achieved through controlled fabrication steps that create regions of varying thickness without requiring complex post-processing or additional via formation steps, thereby managing fabrication complexity while achieving sensitivity improvement.
Solution Approach 2:
The thickness parameter of the interlayer dielectric layer is varied spatially to achieve different sensitivity levels in different regions. This parameter change is implemented through controlled deposition conditions or selective material addition during fabrication, allowing sensitivity optimization without fundamentally changing the fabrication process complexity.
3Reliability
If the via width is increased to maintain electrical connection through thicker dielectric, then the electrical connection is maintained, but the device area increases
Solution Approach 1:
The via structure is segmented into multiple via regions, each connecting to interlayer dielectric regions of different thicknesses. This segmentation allows via width to be optimized locally - vias in thinner regions can be narrower while maintaining reliable electrical connection, reducing overall device area while preserving connection reliability where needed.
Solution Approach 2:
Different via regions are designed with different width characteristics matched to their local dielectric thickness. Vias connecting to thinner dielectric regions use narrower widths sufficient for reliable connection, while vias in thicker regions can accommodate larger widths if needed. This local quality matching maintains electrical connection reliability without unnecessarily increasing device area.
Data Source
AI summary
Embodiments of the disclosure relate to a semiconductor device. The semiconductor device includes a semiconductor substrate, a first metal wiring layer disposed on the semiconductor substrate, an interlayer dielectric layer (ILD) disposed on the first metal wiring layer, a second metal wiring layer disposed on the interlayer dielectric layer, and a first via and a second via disposed in the interlayer dielectric layer. The second via is on the first via, and there is not any metal wiring layer in the interlayer dielectric layer.