Fingerprint Sensor Electrode Stacking for Parasitic Capacitance

The patent introduces a vertical stacking dimension by placing the first and second electrodes at different heights above the substrate, rather than expanding horizontally. This allows increased effective distance between electrodes (improving sensitivity) while maintaining a compact planar footprint (avoiding complexity increase). The sensing electrode, first electrode, and second electrode are arranged in multiple layers above the substrate, utilizing the third dimension to resolve the contradiction.

The patent introduces a low-k insulating layer as an intermediary between the first electrode and the second electrode. This insulating layer serves multiple functions: it electrically isolates the electrodes, reduces parasitic capacitance through its low dielectric constant, and provides a stable fabrication platform that reduces manufacturing precision requirements. By mediating the interaction between electrodes, the system achieves reduced overlapped area (improved sensitivity) without proportionally increasing manufacturing difficulty.

The patent changes the dielectric parameter (k-value) of the insulating material between the first and second electrodes by selecting low-k materials with dielectric constants significantly lower than conventional materials. This parameter change reduces parasitic capacitance between electrodes, thereby improving sensitivity. The low-k insulating layer is integrated into the existing multi-layer electrode structure, achieving parameter optimization without substantially increasing device complexity.