Fingerprint Sensor Pixel Structure for Light Shielding and Low Parasitics
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Solution Overview
Problem
Fingerprint sensors face reliability and sensitivity issues due to external light interference and parasitic capacitances, which degrade their performance in detecting fingerprints and touch inputs.
Innovation Solution
The design incorporates a fingerprint sensor with a specific structure featuring transistors with light shielding conductive second gate electrodes and a capacitor configuration that minimizes parasitic capacitance, enhancing operational stability and sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor structures are used in fingerprint sensors, then device complexity is reduced, but reliability deteriorates due to external light interference and parasitic capacitances
Solution Approach 1:
The transistor gate is segmented into two separate gate electrodes (first gate electrode and second gate electrode) that can be independently controlled. This segmentation allows the first gate to control channel formation while the second gate shields against external light interference, thereby improving reliability without requiring complete structural redesign
Solution Approach 2:
The second gate electrode acts as an intermediary element between the external environment and the channel region. It provides light shielding protection to the channel while maintaining electrical control capabilities, serving as a mediator that protects the sensitive channel region from external light interference
2Measurement precision
If standard capacitor configurations are used, then device complexity is minimized, but measurement precision deteriorates due to parasitic capacitances affecting detection accuracy
Solution Approach 1:
The capacitor structure is designed with specific local characteristics: the first electrode is positioned to minimize overlap with signal lines, and the second electrode is configured to reduce parasitic capacitance with adjacent conductors. This localized optimization of electrode placement and configuration reduces parasitic capacitances without requiring complete redesign of the entire device
Solution Approach 2:
The capacitor electrodes are arranged in a stacked configuration along the vertical dimension rather than side-by-side in the planar dimension. This three-dimensional arrangement reduces the parasitic capacitance between capacitor electrodes and adjacent signal lines, improving measurement precision by exploiting the vertical space above and below the substrate
3Reliability
If dual-gate transistor structures are implemented, then reliability improves through light shielding, but manufacturing precision requirements increase
Solution Approach 1:
The first gate electrode is merged with the scan line structure, and the second gate electrode is merged with the power line structure. This merging approach uses existing conductive layers for multiple purposes, reducing the need for additional separate gate structures and thereby lowering manufacturing precision requirements while maintaining light shielding effectiveness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the reliability and sensitivity of the fingerprint sensor by reducing the impact of external light and parasitic capacitances, leading to more accurate fingerprint detection and touch input recognition.
Implementation Method 1
Each of the second gate electrodes of the first, second, and third transistors may be configured with a light shielding conductive layer
Data Source
AI summary
A fingerprint sensor includes a sensor pixel arranged in a sensing area, including a pixel electrode coupled to a first node; a first transistor coupled between the first node and a first or second power line, the first transistor including a first gate electrode coupled to a first scan line and a second gate electrode opposite to the first gate electrode; a first capacitor coupled between the first node and a second scan line; a second transistor coupled between a readout line and the first power line, the second transistor including a first gate electrode coupled to the first node and a second gate electrode opposite to the first gate electrode; and a third transistor coupled between the second transistor and the first power line, the third transistor including a first gate electrode coupled to the second scan line and a second gate electrode opposite to the first gate electrode.


