Fingerprint Sensor Pixel Circuit for Light and Parasitic Capacitance Control

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Solution Overview

Problem

Existing fingerprint sensors face challenges in achieving high sensitivity and reliability due to external light interference and parasitic capacitances, which can deteriorate their performance.

Innovation Solution

The proposed fingerprint sensor employs a unique configuration of transistors and capacitors, including light shielding conductive layers for the second gate electrodes, which are coupled to the source electrodes of the transistors. This design stabilizes the operational characteristics of the transistors and reduces parasitic capacitances, thereby enhancing sensitivity and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional transistor configuration is used in fingerprint sensor, then device complexity is reduced, but sensitivity and reliability deteriorate due to external light interference and parasitic capacitances

Engineering Contradiction:
Improvesensitivity and reliabilityVSAvoidtransistor configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The transistor is divided into multiple gate electrodes (first gate electrode and second gate electrode) that can be independently controlled. The first gate electrode is coupled to a scan line while the second gate electrode is coupled to a power line, allowing separate control of channel formation and threshold voltage adjustment. This segmentation enables independent optimization of transistor operation to reduce parasitic capacitance effects and improve sensitivity without requiring entirely new device structures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the electrical parameters of the transistor by applying different voltages to the first and second gate electrodes. The first gate electrode voltage controls the main current flow while the second gate electrode voltage adjusts the threshold voltage dynamically. This parameter control mechanism allows optimization of the transistor's electrical characteristics to minimize parasitic capacitance and improve fingerprint detection sensitivity while maintaining conventional device architecture.

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If second gate electrodes are configured with light shielding conductive layers, then external light interference is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improveexternal light interferenceVSAvoidmanufacturing process complexity
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The light shielding function is merged with the existing second gate electrode structure. The second gate electrode is formed using the same conductive material layers that provide light shielding in conventional display structures. By integrating the light shielding function into the already-present gate electrode rather than adding separate shielding layers, the patent reduces external light interference while avoiding additional manufacturing steps.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The second gate electrode serves multiple functions simultaneously: it controls the transistor threshold voltage through electrical connection to the power line, and it provides light shielding through its conductive material properties. This multi-functionality eliminates the need for dedicated light shielding structures, maintaining ease of manufacture while effectively blocking external light interference from affecting the fingerprint sensor operation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If multiple transistors and capacitors are configured per sensor pixel, then sensitivity is improved through reduced parasitic capacitances, but device complexity increases

Engineering Contradiction:
Improvefingerprint detection sensitivityVSAvoidsensor pixel circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extends the conventional planar circuit layout into the vertical dimension by stacking multiple gate electrodes and capacitor structures. The first and second gate electrodes are positioned at different vertical levels within the transistor structure, and capacitors are integrated in overlapping regions. This three-dimensional arrangement allows multiple functional elements to coexist in a compact space, improving sensitivity through reduced parasitic capacitance while maintaining a relatively simple two-dimensional footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The capacitor structures are nested within the transistor regions by positioning capacitor electrodes in overlapping areas with transistor components. The capacitor's first electrode is coupled to the scan line while the second electrode is coupled to the power line, with capacitor regions nested between or alongside transistor structures. This nesting approach integrates multiple functional elements without requiring separate dedicated spaces, thereby improving measurement precision while controlling overall device complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS12216866B2Fingerprint sensor and display device including the same
Publication Date: 2025.02.04 SAMSUNG DISPLAY CO LTD
  • US12216866B2 patent drawing
  • US12216866B2 patent drawing
  • US12216866B2 patent drawing

AI summary

A fingerprint sensor includes a sensor pixel arranged in a sensing area, including a pixel electrode coupled to a first node; a first transistor coupled between the first node and a first or second power line, the first transistor including a first gate electrode coupled to a first scan line and a second gate electrode opposite to the first gate electrode; a first capacitor coupled between the first node and a second scan line; a second transistor coupled between a readout line and the first power line, the second transistor including a first gate electrode coupled to the first node and a second gate electrode opposite to the first gate electrode; and a third transistor coupled between the second transistor and the first power line, the third transistor including a first gate electrode coupled to the second scan line and a second gate electrode opposite to the first gate electrode.