Finite-Field Arithmetic Pipeline for Faster Signature Verification
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Solution Overview
Problem
Existing signature verification processes in finite fields are hindered by slow arithmetic operations, particularly in multiple-precision arithmetic, leading to performance deterioration due to sequential processing of comparisons and subtractions.
Innovation Solution
An arithmetic device that performs modular arithmetic on a finite field by reading out comparison results in advance, allowing parallel processing of arithmetic operations using a hardware processor, including an input unit, an adder/multiplier, a comparator, and an output unit, to enhance computational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple-precision arithmetic operations are performed for signature verification on finite fields, then computational accuracy is maintained, but processing speed deteriorates and computational cost increases
Solution Approach 1:
The patent segments the finite field arithmetic operations into distinct modular components: modular addition, modular subtraction, and modular multiplication. Each operation is implemented as a separate functional unit with dedicated hardware circuits, allowing independent optimization and parallel execution. This segmentation enables the system to maintain computational accuracy through proper modular arithmetic while improving processing speed by eliminating the overhead of general-purpose multiple-precision arithmetic routines.
Solution Approach 2:
The patent changes the parameter representation by working directly with values in the range [0, P-1] for modular operations, where P is the characteristic of the finite field. Instead of using traditional multiple-precision arithmetic with fixed word sizes, the system adapts its computational parameters to the specific requirements of finite field arithmetic, performing operations modulo P at each step. This parameter adaptation maintains mathematical correctness while reducing computational complexity.
2Reliability
If multiple-precision arithmetic operations are performed for signature verification on finite fields, then computational correctness is ensured, but device complexity increases
Solution Approach 1:
The patent extracts the essential modular arithmetic operations from the broader context of multiple-precision arithmetic. By isolating and implementing only the necessary modular addition, subtraction, and multiplication operations specific to finite field arithmetic, the system eliminates the unnecessary complexity of general multiple-precision routines. This extraction maintains computational correctness for finite field operations while reducing device complexity by removing redundant computational mechanisms.
Solution Approach 2:
The patent creates universal modular arithmetic units that can handle different operations (addition, subtraction, multiplication) within the finite field GF(P). These multi-functional units are designed to work with any characteristic P, making the arithmetic device adaptable to different finite field requirements without requiring separate specialized circuits for each operation type. This universality reduces overall device complexity while ensuring computational correctness across various cryptographic applications.
Data Source
AI summary
According to an embodiment, an arithmetic device outputting an arithmetic result on a finite field with characteristic P includes a hardware processor. The hardware processor performs readout processing of a plurality of input values. The hardware processor performs, for each word, arithmetic operations with respect to the plurality of input values by using a value being based on the characteristic P and a comparison value between each input value of the plurality of input values and the characteristic P. The hardware processor outputs a first output value resulting from computing a value being based on each input value of the plurality of input values, the comparison value, and the characteristic P. The hardware processor outputs a second output value resulting from comparing the first output value and the characteristic P.