Finite-Field Decoder Architecture for Area-Latency Tradeoffs
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Solution Overview
Problem
Existing data processing systems for decoding error correction codes, such as BCH and RS codes, face challenges in balancing area and processing latency, with fully parallel implementations requiring large area and high logic circuit delay, while fully serial implementations have increased decoding latency and larger data buffer sizes.
Innovation Solution
A data processing system utilizing an inverse-free Berlekamp-Massey algorithm with a architecture that includes (t+1) finite field multipliers and (t+1) finite field processing units, performing parallel operations with serial components to calculate error locator and evaluator polynomials, achieving a favorable area-latency product and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fully parallel processing architecture is used to implement the Berlekamp-Massey algorithm, then processing speed is improved, but area and logic circuit delay increase significantly
Solution Approach 1:
The patent segments the Berlekamp-Massey algorithm into two distinct phases: a parallel syndrome computation phase that processes multiple syndromes simultaneously, followed by a serial key equation solving phase that processes the error locator polynomial coefficients sequentially. This segmentation allows the system to exploit parallelism where it is most beneficial (syndrome computation) while using serial processing for the more area-intensive key equation solving, thereby resolving the contradiction between processing speed and area.
2Area of stationary object
If a fully serial processing architecture is used to implement the Berlekamp-Massey algorithm, then area and logic circuit delay are reduced, but decoding latency increases
Solution Approach 1:
The patent divides the decoding process into two segments: parallel syndrome computation that reduces overall processing time, and serial key equation solving that minimizes area. The parallel phase computes all syndromes simultaneously, preventing time loss, while the serial phase solves the key equation with minimal area. This segmentation resolves the contradiction between area and decoding latency.
3Loss of time
If a fully parallel processing architecture is used, then processing latency is reduced, but data buffer sizes and area increase
Solution Approach 1:
The patent segments the processing pipeline so that parallel syndrome computation can be performed with minimal buffering, followed by serial key equation solving that requires even less buffer space. By separating the parallel and serial phases, the system achieves low processing latency without requiring large data buffers, resolving the contradiction between processing latency and data buffer size.
Data Source
AI summary
Embodiments of the present invention relate to a data processing system comprising a first arithmetic unit comprising at least one finite field multiplier and at least one finite field adder for selectively performing at least two finite field arithmetic calculations; the data processing system comprising means to use a previous finite field arithmetic calculation result in a current finite field arithmetic calculation to determine at least part of a polynomial.