Finite State Machine Look-Ahead Cascade Architecture
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Solution Overview
Problem
Existing finite state machine (FSM) circuits face challenges in meeting high throughput requirements for high-speed applications, such as 400 Gb/s, due to increased critical path length when cascading multiple FSMs to process wide data buses, which complicates meeting timing requirements at clock rates above 300 MHz.
Innovation Solution
The implementation of a finite state machine circuit with look-ahead-cascade modules, merge modules, and disambiguation modules that process data in parallel, reducing latency and critical path length through a pipelined tree architecture, allowing for high-throughput data processing with a scalable and modular design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple copies of the same FSM circuit are cascaded to process multiple data blocks per clock cycle, then throughput is increased, but the critical path length is linearly increased which negatively offsets the throughput increase
Solution Approach 1:
The FSM circuit is segmented into multiple independent state machine instances (first FSM instance, second FSM instance, etc.), each processing a portion of the wide data bus. This segmentation allows parallel processing of multiple 64-bit data blocks simultaneously while keeping each individual FSM's critical path length manageable, thus achieving high throughput without linearly increasing the critical path.
Solution Approach 2:
The patent transitions from a sequential single-FSM architecture to a parallel multi-FSM architecture, effectively adding a dimensional aspect of parallelism. By utilizing multiple FSM instances operating concurrently on different segments of the data bus, the system achieves throughput scaling without proportionally increasing the critical path length, as each FSM operates independently in its own timing domain.
2Productivity
If multiple copies of the same FSM circuit are cascaded to process multiple data blocks per clock cycle, then more data blocks are processed per clock cycle, but timing requirements at clock rates above 300 MHz cannot be met
Solution Approach 1:
The data bus is segmented into multiple 64-bit portions, with each FSM instance processing one portion independently. This segmentation ensures that each FSM's timing requirements can be met individually even at high clock rates above 300 MHz, while the overall system achieves high productivity through parallel processing of multiple data blocks simultaneously.
Solution Approach 2:
Each FSM instance is optimized with local quality characteristics tailored to its specific processing portion, allowing each instance to meet timing requirements independently. The parallel architecture ensures that timing compliance is achieved locally at each FSM level while collectively achieving high throughput across the entire system.
3Productivity
If a wide data bus is used to process a large amount of data per clock cycle, then throughput is increased, but the critical path length increases making it difficult to meet timing requirements
Solution Approach 1:
The wide data bus is divided into multiple smaller data portions, with each FSM instance processing a specific segment in parallel. This segmentation approach maintains high overall throughput by processing large amounts of data simultaneously while keeping each individual processing path's critical path length short and manageable.
Solution Approach 2:
The patent introduces parallelism as an additional dimension to data processing, transforming the traditional single-path wide-bus approach into a multi-path parallel architecture. This dimensional change allows the system to achieve high data throughput by distributing the processing load across multiple independent paths, each with controlled critical path length.
Data Source
AI summary
In an FSM circuit, look-ahead-cascade modules are coupled to receive possible states and corresponding subsets of data inputs. Merge modules are coupled to a second-to-the-lowest to highest order of the look-ahead-cascade modules. The second-to-the-lowest to highest order of disambiguation modules are coupled to at least a portion of the merge modules. The lowest order of the disambiguation modules is coupled to the lowest order of the look-ahead-cascade modules. The lowest-to-highest order of the disambiguation modules are coupled to receive respective sets of interim states of rN states each to select respective sets of next states of r states each. A state register is coupled to receive a portion of the highest order of the sets of next states to provide a select signal. Each of the disambiguation modules is coupled to receive the select signal for selection of the sets of next states of the r states each.