FinFET Source-Drain Recess Shaping for Dislocation Control
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Solution Overview
Problem
As semiconductor devices, such as FinFETs, undergo miniaturization, they face challenges with misfit dislocations in source/drain regions leading to relaxation and reduced performance, which affects integration density and yield.
Innovation Solution
A method is developed to form non-relaxed source/drain regions by creating U-shaped recesses and reshaping them into V-shaped recesses with stair-like patterns, reducing misfit dislocations through anisotropic and isotropic etching processes, followed by epitaxial growth of source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If source/drain regions are formed through conventional epitaxial growth, then device integration density is improved, but misfit dislocations occur leading to relaxation and reduced device performance
Solution Approach 1:
The patent performs preliminary shaping of recesses into V-shaped profiles with stair-like patterns before epitaxial growth. This preliminary structural preparation reduces misfit dislocations during subsequent material deposition, preventing relaxation and maintaining device performance while enabling continued integration density improvements.
Solution Approach 2:
The patent changes the geometric parameters of the recess structure from conventional shapes to V-shaped profiles with specific stair-like patterns. By optimizing the angle and step dimensions of these recesses, the patent controls stress distribution and dislocation formation during epitaxial growth, resolving the contradiction between high integration density and device reliability.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated, but misfit dislocations and relaxation increase
Solution Approach 1:
The patent applies local quality by creating non-uniform V-shaped recess profiles with stair-like patterns in specific regions where source/drain regions will form. This localized structural modification addresses dislocation issues at critical interfaces without affecting overall device scaling, enabling continued reduction of minimum feature size while maintaining manufacturing precision.
3Ease of manufacture
If conventional etching processes are used to form recesses, then source/drain regions can be formed, but misfit dislocations occur causing relaxation
Solution Approach 1:
The patent performs preliminary anisotropic etching to create V-shaped recesses with stair-like patterns before isotropic etching and epitaxial growth. This preliminary action establishes a stress-optimized geometry that prevents misfit dislocations during subsequent processing, maintaining reliable stress characteristics while preserving ease of manufacture through established etching techniques.
Solution Approach 2:
The patent employs a composite etching approach combining anisotropic and isotropic etching processes. The anisotropic etching creates the V-shaped framework, while isotropic etching refines the structure, resulting in a composite recess profile that optimizes both manufacturability and stress characteristics to prevent relaxation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances stress characteristics in the channel regions, improving FinFET performance and increasing the yield of good devices by minimizing misfit dislocations in source/drain regions.
Implementation Method 1
An anisotropic etching process is performed on the exposed portion of the upper portion of the strip to form a first recess
Implementation Method 2
An isotropic etching process is performed on sidewalls and a bottom surface of the first recess to form a reshaped first recess
Implementation Method 3
source/drain regions are epitaxially grown in the reshaped first recess
Data Source
AI summary
A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the fin. A dummy gate structure is formed over the fin. The fin adjacent the dummy gate structure is recessed to form a first recess. The first recess has a U-shaped bottom surface. The U-shaped bottom surface is below a top surface of the isolation region. The first recess is reshaped to form a reshaped first recess. The reshaped first recess has a V-shaped bottom surface. At least a portion of the V-shaped bottom surface comprises one or more steps. A source/drain region is epitaxially grown in the reshaped first recess.


