FinFET Source/Drain Contact Airgap Spacer Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices progress to smaller technology nodes, the decreasing fin pitch poses significant constraints on materials used between metal gate stacks and neighboring source/drain contacts, necessitating the incorporation of low dielectric constant materials like low-k dielectrics or air gaps to minimize parasitic capacitance, but existing methods have not been fully satisfactory in reducing capacitance effectively.
Innovation Solution
The formation of two sequentially formed air gaps between the source/drain contact and the gate stack, which can be misaligned or partially filled with a dielectric layer of lower dielectric constant than the spacers, and in some cases, these air gaps merge to further reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If traditional materials are used between gate stacks and source/drain contacts, then device structure is simpler, but parasitic capacitance is high
Solution Approach 1:
The patent divides the spacing structure into multiple segments: air gaps, low-k dielectric layers, and spacer layers are sequentially arranged between the source/drain contact and gate stacks. This segmented approach allows each layer to contribute differently to capacitance reduction while maintaining manufacturability, resolving the contradiction between reducing parasitic capacitance and maintaining structural simplicity.
Solution Approach 2:
The patent employs a composite structure combining multiple materials with different dielectric properties: air (lowest k-value), low-k dielectric materials, and standard dielectric spacers. This composite material strategy enables progressive capacitance reduction through the stack while balancing structural complexity and manufacturing feasibility.
2Object-affected harmful factors
If air gaps are introduced to reduce parasitic capacitance, then capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent forms air gaps and low-k dielectric layers before completing the source/drain contact formation. This preliminary action allows the capacitance-reducing structure to be established early in the fabrication process, simplifying subsequent steps and reducing overall manufacturing complexity while achieving the desired capacitance reduction.
Solution Approach 2:
The patent introduces spacer layers as intermediary structures between the air gaps/low-k dielectric and the gate stacks. These spacers serve as manufacturing handles that facilitate the formation of complex structures through standard deposition and etching processes, bridging the gap between the desired air gap structure and manufacturable processes.
3Productivity
If fin pitch is decreased to increase functional density, then production efficiency increases, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality modification by introducing air gaps and low-k dielectric materials specifically in the regions between gate stacks and source/drain contacts, where parasitic capacitance is most critical. This localized approach allows functional density to increase through pitch reduction while capacitance is reduced in the specific high-impact regions, resolving the contradiction between productivity and harmful factors.
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first gate stack, a second gate stack, a first source/drain feature disposed between the first and second gate stacks, and a source/drain contact over and electrically coupled to the first source/drain feature. The source/drain contact is spaced apart from each of the first and second gate stacks by an inner spacer disposed on sidewalls of the source/drain contact, a first air gap, a first gate spacer, and a second air gap separated from the first air gap by the first gate spacer.