FinFET Source/Drain Contact Spacer Width Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing multi gate transistor structure in semiconductor devices faces challenges in preventing shorts between the gate and source/drain contacts, particularly due to the short channel effect, which affects the channel region's potential and current controlling capability.
Innovation Solution
A semiconductor device design that incorporates a spacer layer to prevent shorts between the gate and source/drain contacts, utilizing high selectivity etching through an ion implantation process to secure the source/drain profile, with a specific configuration of contact regions and spacers to ensure accurate placement and width ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate length is reduced to improve current controlling capability, then the current controlling capability is improved, but the short channel effect increases
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional multi-gate structure (FinFET or nanowire). By adding vertical dimension and wrapping the gate around the channel, the effective gate control is enhanced without reducing the horizontal gate length, thus maintaining low SCE while achieving good current control.
Solution Approach 2:
The gate structure is nested around the channel region in a multi-gate configuration. The gate wraps around the FinFET channel or nanowire channel from multiple sides, providing enhanced electrostatic control over the channel potential without requiring gate length reduction.
2Reliability
If a spacer layer is added to prevent short between gate and source/drain contact, then short prevention is improved, but device complexity increases
Solution Approach 1:
The spacer layer is formed in advance during the fabrication process, conformally coating the gate structure before source/drain contact formation. This preliminary spacer deposition ensures proper isolation geometry is established early in the process sequence.
Solution Approach 2:
The spacer layer acts as an intermediary element between the gate structure and the source/drain contact. It provides physical separation and electrical isolation, preventing direct contact and potential shorts while allowing both components to function independently.
3Manufacturing precision
If high selectivity etching is used to secure source/drain profile, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent employs etching processes with high selectivity ratios between different materials (e.g., silicon nitride vs. silicon oxide). By carefully controlling etch parameters such as chemistry composition, temperature, and power, precise source/drain profiles are achieved with clean interfaces and minimal damage to surrounding structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents shorts and secures the source/drain profile, enhancing the current controlling capability and reducing the short channel effect, thereby improving the overall performance of the semiconductor device.
Implementation Method 1
high selectivity etching using an ion implantation process
Data Source
AI summary
A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction.