FinFET Source Drain Epitaxy Doping Process
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Solution Overview
Problem
The non-planar nature of finFETs complicates the doping process during fabrication, leading to issues like shadowing effects, increased tool complexity, and reduced circuit density due to the need for tilt-angle implants or plasma doping, which have limitations in doping control and concentration.
Innovation Solution
The process involves etching a fin on a semiconductor wafer, forming a gate stack with an insulating layer and conductive gate material, and growing epitaxial semiconductor on the channel region's sides to create source and drain epitaxy regions, which are doped in-situ to reduce resistance and apply strain, thereby improving electron or hole mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If tilt-angle implants are used to dope vertical sidewalls of finFET source/drain regions, then doping coverage is improved, but tool complexity and processing time increase
Solution Approach 1:
Instead of tilting the implantation angle to access vertical sidewalls, the patent inverts the approach by growing epitaxial silicon vertically to fill the source/drain regions. This eliminates the need for complex tilt-angle implantation while achieving complete doping coverage through the epitaxial growth process that naturally conforms to the fin structure.
Solution Approach 2:
The patent replaces the mechanical tilt-angle implantation system with an epitaxial growth process. Instead of using a complex implanter mechanism that requires precise angular positioning and multiple orientations, the solution uses chemical vapor deposition or similar epitaxial techniques to grow doped silicon regions, substituting a simpler chemical process for a complex mechanical one.
2Manufacturing precision
If multiple implant angles are used to overcome shadowing effects, then doping uniformity is improved, but processing time increases
Solution Approach 1:
Rather than performing multiple implantation steps at different angles to achieve uniform doping, the patent inverts the sequence by first forming the gate and then growing epitaxial source/drain regions that are inherently uniform. The epitaxial growth process naturally produces consistent doping throughout the volume, eliminating the need for multiple time-consuming implantation steps.
3Object-affected harmful factors
If design rules increase structure spacing to minimize shadowing, then shadowing effects are reduced, but circuit density decreases
Solution Approach 1:
The patent replaces the mechanical constraint of increased spacing with an epitaxial growth process that can fill source/drain regions completely regardless of fin spacing. This substitution allows tight pitch scaling without shadowing issues, as the chemical growth process conforms to the available space rather than requiring line-of-sight access.
4Device complexity
If plasma doping is used as alternative to tilt-angle implants, then tool complexity is reduced, but doping control and concentration limits are worsened
Solution Approach 1:
The epitaxial growth process is self-regulating in terms of doping control. The dopant is incorporated during the growth process itself, allowing precise control of doping concentration through growth rate and temperature management. The process inherently maintains uniform doping throughout the source/drain regions without requiring complex external control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach avoids tilt-angle and plasma implants, ensuring consistent heavy doping, reducing source and drain resistances, and enhancing channel mobility by applying strain, resulting in more efficient finFET fabrication with improved performance.
Implementation Method 1
Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region
Implementation Method 2
The source and drain epitaxy regions may apply a strain to the channel region to improve the mobility of electrons or holes in the channel region
Data Source
AI summary
A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.