FinFET Source/Drain Multi-Sloped Undersurface
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, they face challenges such as increased gate-to-drain capacitance and RC delay, which affect device speed and integration density, necessitating improved methods for forming source/drain regions with reduced volume and cross-sectional area.
Innovation Solution
The process involves epitaxially growing a first layer in a recess of a semiconductor fin, followed by an etch back process, and then growing a second epitaxial layer, allowing adjacent source/drain regions to merge at a higher distance above the substrate, thereby reducing the cross-sectional area of the merged source/drain region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If source/drain regions are formed with conventional methods, then manufacturing process is simple, but gate-to-drain capacitance is high and device speed is limited
Solution Approach 1:
The source/drain region formation is divided into multiple stages: forming recesses in fins, selective epitaxial growth in recesses, and merging regions. This segmentation allows precise control of the merged source/drain region geometry to reduce gate-to-drain capacitance while maintaining manufacturability through standardized process modules
Solution Approach 2:
The invention transitions from planar source/drain regions to three-dimensional merged regions that extend between adjacent fins. By utilizing the vertical dimension and creating regions that merge above the substrate level, the design reduces cross-sectional area and gate-to-drain capacitance while adding geometric complexity that is managed through the segmented approach
2Productivity
If feature size is reduced to increase integration density, then more components fit in given area, but gate-to-drain capacitance increases and RC delay worsens
Solution Approach 1:
The merged source/drain regions are formed with locally optimized geometry where the cross-sectional area is reduced in critical areas adjacent to the gate. This local geometric optimization reduces gate-to-drain capacitance specifically where it impacts speed, while maintaining overall integration density through continued miniaturization
3Speed
If source/drain region volume is reduced, then gate-to-drain capacitance decreases and device speed improves, but manufacturing precision requirements increase
Solution Approach 1:
Recesses are formed in the fins before epitaxial growth, pre-defining the geometry where merged source/drain regions will form. This preliminary structuring guides the subsequent epitaxial growth to achieve the desired reduced cross-sectional area and multi-sloped configuration, reducing the precision requirements of the growth process itself
Solution Approach 2:
Selective epitaxial growth is used where the material grows automatically in the recesses and merges with adjacent regions based on the predefined geometry. The process self-organizes to create the multi-sloped undersurface configuration, reducing the need for complex external control while achieving high geometric precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate-to-drain capacitance, enhances device speed by minimizing RC delay, and improves switching performance, while allowing for increased integration density.
Implementation Method 1
epitaxially growing a first layer in a recess of a semiconductor fin, followed by an etch back process, and then growing a second epitaxial layer
Data Source
AI summary
A device includes a first fin and a second fin extending from a substrate, the first fin including a first recess and the second fin including a second recess, an isolation region surrounding the first fin and surrounding the second fin, a gate stack over the first fin and the second fin, and a source/drain region in the first recess and in the second recess, the source/drain region adjacent the gate stack, wherein the source/drain region includes a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface that is below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface that is above the first height has a second slope that is greater than the first slope.