FinFET External Resistance Reduction via Segmented Epitaxial Source-Drain
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Solution Overview
Problem
Conventional finFET devices face performance issues due to parasitic capacitance and resistance in the source-drain region, which impede current flow and device performance as dimensions shrink below 20 nm.
Innovation Solution
The method involves forming a finFET device with a dual epitaxial source-drain region, where a first epitaxial layer is positioned close to the channel and a second epitaxial layer is shielded by a second spacer to reduce capacitance from the gate, thereby minimizing external resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source-drain region is positioned close to the channel to reduce parasitic resistance, then the external resistance is reduced, but the capacitance from the gate to the source-drain increases
Solution Approach 1:
The source-drain region is divided into two separate epitaxial regions: a first epitaxial source-drain region positioned close to the channel and a second epitaxial source-drain region positioned farther away. This segmentation allows the first region to provide low resistance while the second region is shielded from gate capacitance, thus resolving the contradiction between reducing external resistance and minimizing gate-to-source-drain capacitance.
Solution Approach 2:
A second spacer is introduced as an intermediary structure between the gate and the second epitaxial source-drain region. This second spacer acts as a shield that reduces the capacitive coupling from the gate to the source-drain region, allowing the source-drain to be positioned optimally for low resistance while minimizing the harmful capacitance effect.
2Ease of manufacture
If a single epitaxial source-drain region is formed, then the manufacturing process is simpler, but the external resistance cannot be sufficiently reduced without increasing gate capacitance
Solution Approach 1:
The source-drain region is divided into two separate epitaxial regions formed through a multi-step process involving sequential spacer formation and selective epitaxial growth. This segmentation enables optimized positioning of each region to achieve low external resistance while minimizing gate capacitance, outweighing the increased manufacturing complexity.
Solution Approach 2:
The first spacer is formed preliminarily to define the position of the first epitaxial source-drain region close to the channel. This preliminary structuring enables subsequent selective formation of the second epitaxial region at an optimized distance from the gate, achieving low resistance without excessive capacitance.
3Object-affected harmful factors
If the source-drain region is positioned farther from the channel to reduce gate capacitance, then the capacitance from the gate is reduced, but the external resistance increases
Solution Approach 1:
The source-drain is segmented into two regions with different positioning: the first region is close to the channel for low resistance, while the second region is farther away and shielded by the second spacer to reduce gate capacitance. This segmentation resolves the contradiction by distributing the source-drain function across two optimally positioned regions.
Solution Approach 2:
Different portions of the source-drain structure are given different spatial characteristics: the first epitaxial region is positioned locally close to the channel for optimal electrical contact and low resistance, while the second epitaxial region is positioned locally farther from the gate to minimize capacitive coupling, with each region optimized for its specific function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for reduced external resistance and enhanced device performance by minimizing capacitance and resistance in the source-drain region, enabling better current flow and scalability.
Implementation Method 1
forming an epitaxial source-drain region around a fin, the epitaxial source-drain region having a first epitaxial layer adjacent to and contacting a sidewall of a first spacer and below a second spacer and a second epitaxial layer on the first epitaxial layer
Data Source
AI summary
The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of reducing external resistance within fin field effect transistor (finFET) devices. A first spacer and a second spacer may be formed adjacent to a gate which may reduce capacitance in a substantial portion of a epitaxial source-drain region while also permitting a portion of the epitaxial source-drain region to be located close to a channel. By reducing capacitance from the gate on the substantial portion of the epitaxial source-drain region, resistance in the epitaxial source-drain region may be reduced which may result in increased device performance.