Fin-FET N/P Strength Ratio Tuning via Gate Cut Regions
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Solution Overview
Problem
Conventional fin-FETs face challenges in tuning the N/P strength ratio due to integral fin numbers, making it difficult to achieve varied N/P ratios required for different circuits, as the channel width is typically used to adjust this ratio, which limits the flexibility and efficiency of fin-FETs in integrated circuits.
Innovation Solution
The proposed solution involves configuring fin-FETs with active and dummy gate electrodes, cut regions, and pass-active regions to adjust the effective transistor channel current, allowing for precise tuning of the N/P strength ratio by varying the location and arrangement of cut regions across the gate electrodes, thereby enabling different effective transistor channel currents for each fin-FET in logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the channel width is used to tune the N/P strength ratio, then the N/P ratio can be adjusted, but the flexibility is limited due to integral fin numbers
Solution Approach 1:
The gate electrode is segmented into active gate portions and dummy gate portions. The active gate portions are positioned over the fins to provide gate control, while the dummy gate portions extend beyond the fins to allow independent adjustment of the effective gate width without changing the physical fin count. This segmentation enables continuous tuning of the N/P strength ratio by varying the relative lengths of active versus dummy gate portions, overcoming the discrete nature of fin numbers.
2Power
If multiple fins are used to maximize channel width, then drive current is increased, but the ability to tune N/P ratio precisely is reduced
Solution Approach 1:
The dummy gate portions provide a dynamic adjustment mechanism for the effective gate width. By varying the length of dummy gate portions extending beyond the fins, the effective gate width can be continuously adjusted to achieve precise N/P strength ratios while maintaining the same physical fin configuration that maximizes drive current.
3Adaptability or versatility
If conventional FET width adjustment is used to tune N/P ratio, then the strength ratio can be varied, but the method is not suitable for fin-FET with fixed fin structures
Solution Approach 1:
The dummy gate portions are positioned locally beyond the fin regions, creating a distinction between the active gate area (over the fins) and the dummy gate area (beyond the fins). This local differentiation allows the effective gate width to be adjusted by modifying only the dummy gate portions, leaving the fin structure intact and compatible with existing manufacturing processes.
Data Source
AI summary
The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.