FinFET Single Diffusion Break Multi-Layer Dummy Gate

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Solution Overview

Problem

In fin field effect transistors (finFETs), single diffusion breaks (SDBs) with dummy gates formed after active gate patterning can interfere with downstream device fabrication and increase variability due to differences in processing, unlike double diffusion breaks (DDBs) which consume more space.

Innovation Solution

A finFET with a single diffusion break featuring a multi-layer dummy gate comprising an inactive gate dielectric and conductor layers over a dielectric fill, allowing the dummy gate to be processed similarly to active gates, minimizing interference and variability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If a single diffusion break with dummy gate formed after gate patterning is used, then circuit density is improved, but processing variability and interference with downstream fabrication increase

Engineering Contradiction:
Improvecircuit densityVSAvoidprocessing variability
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The dummy gate structure is prepared in advance with gate dielectric and conductor layers deposited before the diffusion break is formed. This preliminary action ensures that the dummy gate region is pre-configured with the same material layers as active gates, reducing processing variability and eliminating interference with downstream fabrication steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy gate is designed to have the same multi-layer structure (gate dielectric layer and gate conductor layer) as the active gates, making it universal in composition. This allows the dummy gate to be processed simultaneously with active gates using the same deposition processes, improving manufacturing precision while maintaining circuit density.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Area of moving object

If a single diffusion break with dummy gate formed after gate patterning is used, then circuit density is improved, but interference with downstream device fabrication increases

Engineering Contradiction:
Improvecircuit densityVSAvoidinterference with downstream fabrication
Core Design Contradiction:
Area of moving objectVSObject-generated harmful factors

Solution Approach 1:

The gate dielectric layer and gate conductor layer are deposited in advance on the dummy gate region before the diffusion break is formed. This preliminary action ensures that the dummy gate is fully prepared with the same material layers as active gates, eliminating any interference with downstream fabrication processes such as metal gate formation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy gate is designed to have the same multi-layer structure (gate dielectric layer and gate conductor layer) as the active gates, making it universal in composition. This allows the dummy gate to be processed simultaneously with active gates using the same deposition processes, eliminating interference with downstream device fabrication.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If a double diffusion break is used, then processing variability is reduced, but circuit density decreases due to increased space consumption

Engineering Contradiction:
Improveprocessing variabilityVSAvoidcircuit density
Core Design Contradiction:
Manufacturing precisionVSArea of moving object

Solution Approach 1:

The gate dielectric layer and gate conductor layer are deposited in advance on the dummy gate region before the diffusion break is formed. This preliminary action ensures that the dummy gate is fully prepared with the same material layers as active gates, reducing processing variability while maintaining a compact single diffusion break structure that improves circuit density.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10770589B2Fin field effect transistor including a single diffusion break with a multi-layer dummy gate
Publication Date: 2020.09.08 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10770589B2 patent drawing
  • US10770589B2 patent drawing
  • US10770589B2 patent drawing

AI summary

In one example, a fin field effect transistor including a single diffusion break with a multi-layer dummy gate is disclosed. One example of field effect transistor includes a first transistor array comprising a first active gate, a second transistor array comprising a second active gate, and a single diffusion break formed between the first transistor array and the second transistor array, wherein the single diffusion break comprises a dummy gate comprising multiple layers of different materials.