FinFET Channel Stop Imp via Isolation Etch Back

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Solution Overview

Problem

The short channel effect and punch through effect in FinFET devices become significant issues as feature sizes decrease, with dopants diffusing into the channel region during the annealing process after channel stop ion implantation, affecting device performance.

Innovation Solution

A method is developed to reduce dopant diffusion into the channel region by performing an etch back process on the isolation region before annealing, allowing dopants to diffuse outside the isolation region and semiconductor fins, thereby minimizing their impact on the channel region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If channel stop ion implantation is performed to suppress punch through effect, then device reliability is improved, but dopants diffuse into channel region during annealing causing harmful effects

Engineering Contradiction:
Improvepunch through effect suppressionVSAvoiddopant diffusion into channel region
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary action by performing channel stop ion implantation before the annealing process, ensuring dopants are positioned in the isolation region prior to thermal treatment. This sequencing allows the implantation to occur when the structure is intact, preventing subsequent dopant migration into the channel during annealing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the dopants from the channel region by directing ion implantation specifically into the isolation region. The dopants are taken out of potential harm to the channel and placed into the isolation region where they can be activated during annealing without affecting channel performance.

Inventive Principle:
Principle #2Taking out (Extraction)

2Length of moving object

If feature size is reduced to improve device scaling, then device size is decreased, but short channel effect and punch through effect become more significant

Engineering Contradiction:
Improvefeature sizeVSAvoidshort channel effect and punch through effect
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent applies preliminary anti-action by introducing channel stop doping into the isolation region before channel formation issues can develop. This preemptive doping creates a protective effect against short channel and punch through effects that would otherwise become more severe with reduced feature sizes.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent applies local quality by concentrating dopants specifically in the isolation region adjacent to the channel, rather than uniformly throughout the structure. This localized doping provides targeted suppression of punch through effects at the critical isolation-channel interface while maintaining channel integrity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces dopant diffusion into the channel region, enhancing the performance of FinFET devices by mitigating the short channel and punch through effects.

Implementation Method 1

implanting ions into the substrate structure to form a doped region in the at least one semiconductor fin and in the isolation region

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

performing an annealing process to activate the implanted ions in the doped region

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 3

etching back the isolation region to expose a portion of the at least one semiconductor fin

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS10367058B2Channel stop imp for the FinFET device
Publication Date: 2019.07.30 SEMICON MFG INT (SHANGHAI) CORP
  • US10367058B2 patent drawing
  • US10367058B2 patent drawing
  • US10367058B2 patent drawing

AI summary

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, a semiconductor fin on the substrate, and an isolation region on opposite sides of the semiconductor fin, the isolation region having an upper surface substantially flush with an upper surface of the at least one semiconductor fin. The method also includes implanting ions into the substrate structure to form a doped region in the semiconductor fin and in the isolation region, etching back the isolation region to expose a portion of the semiconductor fin, and performing an annealing process to activate the implanted ions in the doped region. Because the annealing is performed after the etching back of the isolation region, a portion of the implanted ions diffuses out of the isolation region and the fin, thereby reducing ion diffusion into the channel region and improving the device performance.