FinFET Gate Trench Formation for Electrical Short Prevention
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Solution Overview
Problem
In the fabrication of integrated circuits, particularly FinFET devices, the reduction in fin size leads to challenges such as fin damage during etching and cleaning processes, and the risk of epi-to-epi shorting and contact-to-gate electrical shorts due to the removal of gate cap and spacer materials during contact formation.
Innovation Solution
The method involves forming a layer of material with a plurality of trenches above the active region, creating laterally spaced-apart source/drain trenches, and then forming a gate trench between these trenches, allowing portions of the material to remain between the source/drain and gate trenches, which enables the formation of a gate structure and cap layer while minimizing material loss and reducing the risk of shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate cap and spacer materials are removed during contact formation to improve device performance, then electrical conductivity is improved, but the risk of contact-to-gate electrical shorts increases
Solution Approach 1:
The patent performs preliminary actions by forming the gate structure and gate cap layer before forming the contact structures. This sequence allows the gate cap to serve as a protective layer during contact formation, preventing electrical shorts while still allowing the gate to function. The gate cap is removed only after contacts are safely formed, eliminating the harmful shorting risk while maintaining conductivity benefits.
Solution Approach 2:
The gate cap layer serves as an intermediary protective element during the contact formation process. It acts as a physical barrier that prevents direct electrical contact between the contact structures and the gate electrode, thereby eliminating the shorting hazard while allowing the underlying gate structure to maintain its electrical function.
2Productivity
If fin size is reduced to increase device density, then the number of devices per chip area increases, but fin damage during etching and cleaning processes increases
Solution Approach 1:
The patent forms the gate structure and gate cap layer before performing etching and cleaning operations. This preliminary gate formation creates a protective framework that shields the reduced-size fins from damage during subsequent processing steps, enabling high device density while maintaining fin integrity.
Solution Approach 2:
The patent changes the temporal parameter of the fabrication process by reordering operations - specifically, performing gate formation before contact formation and protecting fins through the gate cap structure. This parameter change allows aggressive etching and cleaning processes to be used without damaging the scaled-down fins, thereby achieving high device density with maintained reliability.
3Speed
If channel length is decreased to improve switching speed, then operating speed increases, but short channel effects worsen
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate structures (such as FinFET or gate-all-around configurations). This dimensional change provides enhanced gate control over the channel from multiple directions, effectively suppressing short channel effects even when the channel length is significantly reduced for high-speed operation.
Solution Approach 2:
The patent changes the geometric parameters of the gate structure, transitioning from two-dimensional planar gates to three-dimensional structures with increased surface area in contact with the channel. This parameter change maintains effective gate control over shortened channels, enabling high switching speed while mitigating short channel effects through improved electrostatic control.
Data Source
AI summary
One illustrative device disclosed herein includes, among other things, an active region defined in a semiconductor substrate, a layer of material positioned above the substrate, a plurality of laterally spaced-apart source/drain trenches formed in the layer of material above the active region, a conductive source/drain contact structure formed within each of the source/drain trenches, a gate trench formed at least partially in the layer of material between the spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure.