FinFET Memory Cells with Discontinuous Storage Elements
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Solution Overview
Problem
Conventional floating gate nonvolatile memories face inefficiencies in programming mechanisms, such as slow Fowler-Nordheim tunneling and high programming current in hot carrier injection, and challenges in high-density memory fabrication due to defects in gate dielectric layers, which affect data retention and increase manufacturing costs.
Innovation Solution
The development of electronic devices with fins and discontinuous storage elements, where gate electrodes and doped regions are formed with dimensions smaller than lithographic resolution limits, allowing for smaller memory cells and proper electrical fields for source-side injection, and the use of discontinuous storage elements like silicon nanocrystals to enhance programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional hot carrier injection is used for programming, then programming capability is achieved, but programming current is high and efficiency is low
Solution Approach 1:
The patent creates a localized high electrical field region near the source by introducing a lightly-doped extension region and a shallow trench isolation structure. This local field enhancement allows hot carrier generation to occur preferentially near the source, improving injection efficiency into the floating gate while reducing the overall programming current requirement compared to conventional drain-side hot carrier injection
2Area of moving object
If gate dielectric layer thickness is decreased for high density, then memory cell size is reduced, but defects such as pinholes increase causing electrical shorts
Solution Approach 1:
The patent introduces a thin interfacial layer between the silicon substrate and the gate dielectric layer. This interfacial layer acts as a mediator that passivates interface states and prevents defect propagation, allowing the use of thinner gate dielectric layers for high-density memory while maintaining data retention reliability by eliminating electrical shorts caused by pinholes
3Productivity
If source-side injection is used to improve efficiency, then programming efficiency improves, but additional critical lithographic sequences are required increasing device complexity
Solution Approach 1:
The patent combines the source-side injection structure formation with the existing shallow trench isolation process. The lightly-doped extension region is formed simultaneously with the trench isolation, and the source-side injection field enhancement structure is integrated into the same lithographic and etching sequences, thereby achieving improved programming efficiency without adding additional critical lithographic steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of smaller memory cells capable of storing multiple bits of data efficiently, with improved programming mechanisms using conventional hot carrier injection and source-side injection, while reducing manufacturing costs and minimizing defects in the gate dielectric layer.
Implementation Method 1
an electrical field is generated along a channel region of a memory cell. Within the channel region, the electrical field is the highest near the drain region. The electrical field accelerates carriers flowing within the channel region
Implementation Method 2
One or more materials may be used for the gate dielectric layer instead of silicon dioxide
Data Source
AI summary
An electronic device can include a substrate including a fin lying between a first trench and a second trench, wherein the fin is no more than approximately 90 nm wide. The electronic device can also include a first gate electrode within the first trench and adjacent to the fin, and a second gate electrode within the second trench and adjacent to the fin. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and the fin, and the second set of the discontinuous storage elements lies between the second gate electrode and the fin. Processes of forming and using the electronic device are also described.