FinFET Punch-Through Prevention via Segmented Epitaxial Doping

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Solution Overview

Problem

Conventional punch-through stops in FinFET semiconductor devices fail to effectively contain impurities within the fin, leading to a high risk of parasitic current and performance loss due to impurity diffusivity.

Innovation Solution

A method involving the creation of a blanket layer of semiconductor material with impurities over a substrate, followed by masking, epitaxial semiconductor material growth, and etching to form n-type and p-type raised structures, with a middle portion containing impurities and a top portion lacking impurities, surrounded by isolation material.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional implant is used to create punch-through stops, then punch-through risk is reduced, but impurity containment is poor leading to high diffusivity and performance loss

Engineering Contradiction:
Improvepunch-through preventionVSAvoidimpurity containment
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The fin structure is divided into distinct regions: a middle portion containing the punch-through stop with impurities, and top portions with different doping. This segmentation allows the impurities to be confined to specific regions rather than diffusing throughout the entire fin structure, resolving the contradiction between punch-through prevention and impurity containment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the fin are given different doping characteristics - the middle portion has punch-through stop impurities while the top portions have channel doping. This local differentiation ensures that impurities remain contained in their intended regions, preventing the performance loss associated with widespread impurity diffusion while maintaining effective punch-through prevention.

Inventive Principle:
Principle #3Local quality

2Productivity

If channel length is reduced to improve device scaling, then device density increases, but parasitic current from source to drain increases due to punch-through

Engineering Contradiction:
Improvedevice scalingVSAvoidparasitic current
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The punch-through stop is formed in advance during the epitaxial growth process, before subsequent processing steps. This preliminary action ensures that the impurity barrier is already in place to prevent parasitic current, enabling aggressive channel length scaling without the harmful effects of punch-through.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The punch-through stop acts as an intermediary layer between the source and drain regions, preventing direct parasitic current flow. This intermediate structure with controlled impurity content blocks the harmful current path while allowing the channel to be scaled down for improved device density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the risk of punch-through by effectively containing impurities within the FinFET structure, enhancing performance by minimizing parasitic current.

Implementation Method 1

creating epitaxial semiconductor material on an unmasked portion of the structure

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS9847333B2Reducing risk of punch-through in FinFET semiconductor structure
Publication Date: 2017.12.19 GLOBALFOUNDRIES US INC
  • US9847333B2 patent drawing
  • US9847333B2 patent drawing
  • US9847333B2 patent drawing

AI summary

Reducing a chance of punch-through in a FinFET structure includes providing a substrate, creating a blanket layer of semiconductor material with impurities therein over the substrate, masking a portion of the blanket layer, creating epitaxial semiconductor material on an unmasked portion of the structure, removing the mask, and etching the structure to create n-type raised structure(s) and p-type raised structure(s), a bottom portion of the raised structure(s) being surrounded by isolation material. A middle portion of the raised structure(s) includes a semiconductor material with impurities therein, the middle portion extending across the raised structure(s), and a top portion including a semiconductor material lacking added impurities.