FinFET Channel Width Tuning via Segmented Gate and Variable Sidewall Spacers
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Solution Overview
Problem
Fin-type field effect transistors (FinFETs) are limited to channel widths that are integer multiples of the semiconductor fin height, restricting the range of operational characteristics and making it difficult to tune designs for desired operating parameters.
Innovation Solution
The formation of sidewall structures that extend to different heights from the substrate for different transistors, allowing the effective size of the FinFET channel region to be adjusted for specific operating voltages without altering the physical size of the semiconductor fin, by spacing a portion of the gate electrode sufficiently far from the semiconductor fin to prevent channel inversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If FinFETs are formed with channel widths as integer multiples of fin height, then manufacturing precision is improved, but adaptability deteriorates
Solution Approach 1:
The gate electrode is segmented into multiple portions along the channel width direction, with each portion independently controllable. This segmentation allows different gate portions to control different channel width regions, enabling continuous channel width tuning rather than discrete steps based on fin height multiples.
Solution Approach 2:
The gate electrode structure is made dynamically adjustable through the sidewall spacer configuration. By varying the sidewall spacer thickness, the effective gate coverage over the channel can be continuously adjusted, transforming the static channel width determination into a dynamic parameter that can be tuned for different operating characteristics.
2Adaptability or versatility
If sidewall structures are formed at different heights, then adaptability is improved, but device complexity increases
Solution Approach 1:
Different sidewall spacer thicknesses are applied to different gate electrode portions corresponding to different channel width requirements. This local differentiation allows each transistor to be optimized for its specific operating voltage and performance requirements while maintaining a systematic fabrication approach.
Solution Approach 2:
The sidewall spacers are formed as preliminary structures before final gate electrode patterning. This preliminary action establishes the framework for subsequent gate material deposition and patterning steps, enabling precise channel width control to be built into the fabrication process flow rather than added as a separate tuning step.
Data Source
AI summary
An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.