FinFET Source Drain Twin Defect Removal via Segmentation
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Solution Overview
Problem
The existing fabrication process for N-type FinFETs suffers from lattice damage and twin defects in the fin structures due to ion implantations, which affect the transistor's performance, and high temperatures during the process can damage the photoresist layer.
Innovation Solution
The method involves removing the top portions of the fin structures after ion implantations, forming a first semiconductor material layer doped with ions for the source and drain, and a contact-resistance-reducing layer to improve the FinFET's performance by reducing twin defects and enhancing carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is performed to form source and drain regions, then doping is achieved, but lattice damage and twin defects are generated in the fin structures
Solution Approach 1:
The fin structure is divided into two parts: the lower part is retained to maintain structural integrity and provide mechanical support, while the damaged upper part is removed to eliminate twin defects. This segmentation allows the device to benefit from the doped region while avoiding the harmful effects of lattice damage.
Solution Approach 2:
The damaged upper portion of the fin structure containing twin defects is extracted and removed through selective etching. This extraction eliminates the source of reliability issues while preserving the functional doped regions formed by ion implantation.
2Manufacturing precision
If high temperature annealing is performed to activate dopants, then doping efficiency is improved, but photoresist layer is damaged
Solution Approach 1:
The dopant activation annealing is performed before the photoresist-based patterning steps. By completing the high-temperature annealing process earlier in the fabrication sequence, the photoresist layer is not exposed to temperatures that would cause damage, while still achieving complete dopant activation.
3Strength
If complete fin structures are retained to maintain structural integrity, then mechanical strength is preserved, but twin defects cause short circuits
Solution Approach 1:
Different regions of the fin structure are treated differently: the lower region is retained with its original properties to provide mechanical strength, while the upper damaged region is removed to eliminate electrical leakage paths. This local differentiation optimizes both structural and electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of N-type FinFETs by reducing twin defects and contact resistance, leading to better carrier mobility and reduced short circuits, while maintaining the structural integrity of the fin structures.
Implementation Method 1
a lightly doped drain (LDD) ion implantation and a Halo ion implantation are performed on the fin structures 11 on both sides of the gate structure 12
Implementation Method 2
A thermal annealing process is further performed to form an LDD ion implantation region and a Halo ion implantation region in the fin structures 11 on both sides of the gate structure 12
Implementation Method 3
an in-situ doping growth process is performed to form a silicon carbide layer 15 on the fin structures 11
Implementation Method 4
an epitaxial deposition is used to grow a silicon cap (Si-Cap) layer 16 on the silicon carbide layer 15
Implementation Method 5
an annealing process is performed on the metal layer. The metal layer and the Si-Cap layer are melted to form a metal silicide layer
Data Source
AI summary
The present disclosure provides a method for forming a field-effect fin transistor (FinFET) structure. The method includes providing a substrate with fin structures; forming a gate structures across the fin structures; and forming ion implantation regions in the fin structures at both sides of the gate structure. The method also includes removing top portions of the fin structures at both sides of the gate structure to form remaining portions of the fin structures; forming a first semiconductor material layer on the remaining portions of the fin structures; and forming a second semiconductor material layer on the first semiconductor material layer, the second semiconductor material being doped with barrier-lowering ions. The method further includes forming a metal layer on the second semiconductor material layer, and performing an annealing process on the metal layer to form a contact-resistance-reducing layer.