FinFET Dielectric Cap Layer Formation for Void-Free Isolation
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Solution Overview
Problem
The challenge in forming isolation structures on FinFETs and other semiconductor devices is the difficulty in filling trenches with insulating material without creating voids, which can lead to reduced device performance due to the high-temperature anneal process causing silicon consumption and altering fin thickness.
Innovation Solution
A method involving forming trenches in a semiconducting substrate, depositing a layer of insulating material that covers the lower portion of the fin but not the upper portion, applying a protective material to the upper portion, and performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a high-temperature anneal process is used to fill trenches with insulating material, then the trenches can be filled, but silicon consumption occurs and fin thickness is altered
Solution Approach 1:
A cap layer is formed on the fin structure before the anneal process. This cap layer serves as a protective barrier that prevents silicon consumption during the subsequent high-temperature anneal process, thereby maintaining the intended fin thickness while still allowing the anneal to densify the insulating material in the trenches.
Solution Approach 2:
The cap layer acts as an intermediary protective layer between the fin structure and the harsh anneal environment. It mediates the interaction by allowing the anneal process to proceed for densifying the insulating material while blocking the harmful effects that would otherwise consume silicon and alter fin thickness.
2Reliability
If trenches are filled with insulating material, then isolation structures are formed, but voids may be created reducing device performance
Solution Approach 1:
The anneal process parameters (temperature, atmosphere, duration) are optimized to densify the insulating material in the trenches without causing excessive silicon consumption. The cap layer enables these parameter adjustments by protecting the fin structure, allowing the insulating material to be properly densified and void-free while maintaining fin integrity.
3Speed
If the channel length is decreased to improve switching speed, then operating speed increases, but short channel effects are exacerbated
Solution Approach 1:
The cap layer is selectively positioned only on the fin structures that require protection during the anneal process. This localized approach allows the anneal to densify the insulating material in the trenches while preserving the fin dimensions, thereby maintaining reliable electrical characteristics even in devices with reduced channel length where short channel effects are more pronounced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively forms isolation structures without voids, maintaining the intended fin thickness and improving device performance by reducing silicon consumption and enhancing the filling of trenches with insulating material.
Implementation Method 1
performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin
Data Source
AI summary
Disclosed herein are various methods of forming isolation structures on FinFETs and other semiconductor devices, and the resulting devices that have such isolation structures. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define a fin for a FinFET device, forming a layer of insulating material in the trenches, wherein the layer of insulating material covers a lower portion of the fin but not an upper portion of the fin, forming a protective material on the upper portion of the fin, and performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin.