FinFET Diffusion Break Regions for Device Isolation
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Solution Overview
Problem
As semiconductor devices become more highly integrated, achieving high transistor performance is challenging due to variations in field-effect transistor structures, particularly in realizing consistent device characteristics across different regions.
Innovation Solution
The implementation of a semiconductor device design featuring fins with specific geometries and a diffusion break region, where the diffusion break region extends across the fins and includes spacers, to improve device isolation and reduce variation in transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor devices are highly integrated, then device density increases, but transistor performance and device characteristics become more difficult to control and maintain consistency
Solution Approach 1:
The patent applies local quality by introducing a diffusion break region with specific geometric features (protrusions and recesses) at critical locations between adjacent fins. This localized structural modification creates different diffusion characteristics in different regions, allowing control over carrier diffusion while maintaining high device density. The diffusion break region's protrusions extend into the channel region to prevent carrier diffusion, while recesses allow controlled diffusion paths, thus resolving the contradiction between high integration and performance consistency.
2Reliability
If diffusion break regions are added to control carrier diffusion, then device performance improves, but device structure becomes more complex
Solution Approach 1:
The diffusion break region is segmented into multiple functional portions: protrusions extending into the channel region to block carrier diffusion, recesses allowing controlled diffusion paths, and different height levels (first, second, and third portions) to create staged diffusion barriers. This segmentation allows precise control over carrier diffusion while maintaining a systematic structure that can be integrated into existing FinFET architectures, balancing performance improvement with structural complexity.
3Reliability
If device isolation is enhanced to reduce variation, then transistor performance consistency improves, but manufacturing process complexity increases
Solution Approach 1:
The diffusion break region is formed preliminarily during the device fabrication process, before final transistor operation. The protrusions and recesses are created in advance to establish controlled diffusion paths and barriers. This preliminary structuring ensures that carrier diffusion is controlled from the outset, reducing performance variation without requiring additional complex manufacturing steps during device operation or post-fabrication processing.
Data Source
AI summary
A FINFET includes a first fin extending in a first direction on a substrate and, a second fin extending in the first direction and spaced apart from the first fin in the first direction. A third fin is provided with a long side shorter than long sides of the first fin and the second fin and is disposed between the first fin and the second fin. A first gate structure extends in a second direction different from the first direction and crosses the first fin. A device isolation layer is disposed on a lower sidewall of each of the first, second and third fins and is formed to extend in the first direction. An electrically insulating diffusion break region includes a first portion crossing between the first fin and the third fin, a second portion crossing between the second fin and the third fin, and a third portion disposed between the first portion and the second portion on the third fin. The diffusion break region extends in the second direction on the device isolation layer. A level of a lower surface of the third portion is higher than a level of a lower end of each of the first portion and the second portion and is lower than a level of an upper surface of the first gate structure.