FinFET Source Drain Dislocation Fabrication for Carrier Mobility
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Solution Overview
Problem
Current techniques for enhancing stress in metal-oxide-semiconductor (MOS) devices, particularly in Fin Field-Effect Transistors (FinFETs), are inadequate in consistently inducing tensile stress in n-type MOS (NMOS) and compressive stress in p-type MOS (PMOS) devices to improve carrier mobility effectively.
Innovation Solution
The method involves forming FinFETs with dislocation planes in the source and drain regions, using a process that includes semiconductor substrate preparation, etching fin structures, forming Shallow Trench Isolation regions, depositing gate dielectric and electrode layers, patterning, and applying a strained capping layer with annealing to create dislocation planes that extend into the channel regions, thereby inducing desired stresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional stress enhancement techniques are used in MOS devices, then some stress improvement may be achieved, but the stress induction is inconsistent and carrier mobility improvement is insufficient
Solution Approach 1:
The patent changes the physical and chemical parameters of the source/drain regions by forming dislocation planes through controlled annealing processes. The dislocation planes are created by heating the device to specific temperatures (e.g., 800-1100°C) to induce controlled crystal defects that generate mechanical stress in the channel region, thereby improving carrier mobility through parameter transformation rather than conventional stressor structures
Solution Approach 2:
The dislocation planes are localized specifically in the source and drain regions adjacent to the channel, creating local stress fields where needed. This localized stress induction affects only the critical regions for carrier transport while leaving other device regions unchanged, achieving consistent stress enhancement precisely where it impacts carrier mobility
2Reliability
If dislocation planes are formed in source and drain regions through annealing, then carrier mobility is enhanced through optimized stress conditions, but the manufacturing process complexity increases
Solution Approach 1:
The formation of dislocation planes is merged with the existing source/drain region fabrication process. The annealing step that creates dislocation planes is combined with or performed sequentially after standard source/drain formation steps, integrating the stress enhancement process into the conventional manufacturing flow rather than adding completely separate process modules
Solution Approach 2:
The manufacturing process utilizes thermal parameter changes through controlled annealing to transform the crystal structure of source/drain regions. By adjusting temperature, time, and atmospheric parameters during annealing, the desired dislocation planes are formed without requiring additional material deposition or complex patterning steps, thus enhancing carrier mobility while limiting process complexity growth
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility by optimizing stress conditions in the channel regions of FinFETs, leading to improved performance and efficiency in MOS devices.
Implementation Method 1
a strained capping layer is formed over a portion of the source/drain region
Implementation Method 2
applying a strained capping layer with annealing to create dislocation planes that extend into the channel regions
Data Source
AI summary
A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.