Dual-Side Source/Drain Contact Layout for Lower FinFET Resistance

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing contact resistance between source/drain regions and contact structures in semiconductor devices, particularly due to the scaling down of device dimensions, which increases complexity and affects performance and efficiency.

Innovation Solution

The implementation of dual side contact structures with Ru-based liner-free back vias and a stack of metal silicide and nitride layers, which reduces contact resistance by using epitaxially grown semiconductor materials and specific work function metals for n-type and p-type FETs, and forming these structures on both sides of the finFETs to connect to a back-side power rail.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device dimensions are scaled down to increase storage capacity and processing speed, then higher performance and storage capacity are achieved, but contact resistance between source/drain regions and contact structures increases

Engineering Contradiction:

Improveprocessing speedVSAvoidcontact resistance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The contact structure is divided into multiple segments: a first contact structure on the front side and a second contact structure on the back side, with each segment serving specific functions. This segmentation allows optimization of each part independently to reduce overall contact resistance while maintaining scaled dimensions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a third dimension by forming contact structures on both the front and back sides of the finFET. This vertical/dual-sided approach reduces lateral contact resistance constraints imposed by scaling, providing additional current pathways without increasing planar footprint.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If device dimensions are scaled down, then higher storage capacity is achieved, but manufacturing complexity increases

Engineering Contradiction:

Improvestorage capacityVSAvoidmanufacturing process complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The manufacturing process is segmented into distinct stages: forming the first contact structure before finFET fabrication, then forming the second contact structure after finFET fabrication. This segmentation allows each contact structure to be optimized independently and simplifies the overall manufacturing complexity by breaking down the multi-step process into manageable stages.

Inventive Principle:

Principle #1Segmentation

3Reliability

If dual side contact structures are implemented, then contact resistance is reduced and electrical connectivity is enhanced, but device structure complexity increases

Engineering Contradiction:

Improveelectrical connectivityVSAvoidcontact structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Both the first and second contact structures serve dual purposes: providing electrical connectivity and serving as etch stop layers. This multi-functionality reduces the need for additional separate structures, thereby reducing overall device complexity while maintaining enhanced electrical connectivity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Instead of forming all contact structures on the front side (conventional approach), the patent inverts the approach by forming contact structures on both front and back sides. The second contact structure on the back side acts as an etch stop, inverting the traditional role assignment and simplifying the overall structure.

Inventive Principle:

Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in compact, low-resistive contact structures that enhance electrical connectivity and reduce parasitic capacitance, improving the performance and manufacturing efficiency of semiconductor devices.

Implementation Method 1

Ru-based liner-free back vias... reduces contact resistance

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

stack of metal silicide and nitride layers... specific work function metals for n-type and p-type FETs... reduce parasitic capacitance

Methodology Applied

Scientific EffectWork function:

Implementation Method 3

using epitaxially grown semiconductor materials

Methodology Applied

Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS12046634B2Dual side contact structures in semiconductor devices

Publication Date: 2024.07.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.