FinFET Dummy Gate Contour Control via Dopant Gradients
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Solution Overview
Problem
Current FinFET devices face challenges with low device performance and yield due to a small top critical dimension (CD) of the dummy gate, which results in a thin protective layer during subsequent hole formation, leading to inadequate protection and poor performance.
Innovation Solution
A method is developed to form a gate with a large top CD by controlling dopant concentration during doping of the dummy gate and interlayer dielectric (ILD), allowing for a suitable contour that enhances follow-up processes and improves device performance and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the top critical dimension (CD) of the dummy gate is reduced to enable further scaling, then device feature size decreases and production efficiency improves, but the protective layer thickness becomes insufficient leading to poor device performance and yield
Solution Approach 1:
The method performs preliminary actions by forming a mandrel structure with controlled dimensions before the final gate formation. The mandrel is formed with a specific top CD that is larger than the final gate requirement, allowing sufficient protective layer deposition. Subsequent selective removal of the mandrel top portion creates the desired gate profile while maintaining protective layer integrity throughout the process.
Solution Approach 2:
The dummy gate formation process is segmented into multiple stages: first forming a mandrel with controlled top CD, then selectively removing portions of the mandrel, and finally forming the protective layer. This segmentation allows each step to be optimized independently, ensuring the protective layer has adequate thickness while the final gate achieves the required small top CD for scaling.
2Length of moving object
If the top critical dimension (CD) of the dummy gate is reduced, then device geometry scaling is achieved, but the protective layer becomes too thin to protect during subsequent hole formation
Solution Approach 1:
The mandrel is formed in advance with a top CD that provides adequate space for protective layer formation. The protective layer is deposited on the mandrel surface before the mandrel is selectively removed, ensuring the layer has sufficient thickness and mechanical strength to protect underlying structures during subsequent processing steps.
Solution Approach 2:
The mandrel acts as an intermediary structure that enables the formation of a sufficiently thick protective layer. By using the mandrel as a temporary support structure with larger dimensions, the protective layer can be deposited with adequate thickness, and the mandrel is later removed to reveal the final gate structure.
3Ease of manufacture
If dopant concentration in the interlayer dielectric is increased to modify contour, then follow-up processes are enhanced, but manufacturing complexity increases
Solution Approach 1:
The doping process applies different dopant concentrations to different regions of the interlayer dielectric. The dopant concentration is highest adjacent to the mandrel and decreases with distance from the mandrel. This local variation in dopant concentration creates the desired contour modification in the interlayer dielectric without requiring complex multi-step doping processes throughout the entire structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in improved device performance and yield by maintaining a protective layer integrity during hole formation, addressing the limitations of small top CD in current FinFETs.
Implementation Method 1
doping a dopant into the dummy gate and the ILD, in which a surface dopant concentration of the dummy gate is lower than a surface dopant concentration of the ILD
Data Source
AI summary
A FinFET includes a fin structure, a gate, a source-drain region and an inter layer dielectric (ILD). The gate crosses over the fin structure. The source-drain region is in the fin structure. The ILD is laterally adjacent to the gate and includes a dopant, in which a dopant concentration of the ILD adjacent to the gate is lower than a dopant concentration of the ILD away from the gate.