FinFET eDRAM Strap Connection Structure with Insulating Spacer

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Solution Overview

Problem

Existing strap connection structures for embedded dynamic random access memory (eDRAM) in semiconductor devices face challenges in efficiently connecting finFETs to storage capacitors, leading to issues with parasitic current flow and electrical shorting.

Innovation Solution

A strap connection structure is fabricated by forming a buried oxide layer, a deep trench, and a storage capacitor, with a metal strap deposited on the sidewall and capacitor, and a fin formed on the substrate in communication with the metal strap, sealed by a spacer to prevent shorting and parasitic current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a metal strap is deposited to connect finFET to storage capacitor, then electrical connection is improved, but parasitic current flow and electrical shorting occur

Engineering Contradiction:
Improveelectrical connectionVSAvoidparasitic current flow
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

An oxide layer is deposited between the metal strap and the finFET, serving as an intermediary that provides electrical isolation. This prevents parasitic current flow and electrical shorting while maintaining the necessary electrical connection through controlled interfaces, resolving the contradiction between connection reliability and parasitic current prevention.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The connection structure is segmented into distinct functional layers: the metal strap for electrical connection, the oxide layer for isolation, and the finFET for transistor operation. This segmentation allows each component to perform its specific function without interfering with others, preventing parasitic current flow while maintaining effective electrical connection.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If existing strap connection structures are used, then manufacturing process is simplified, but electrical shorting and parasitic coupling increase

Engineering Contradiction:
Improvemanufacturing processVSAvoidelectrical shorting
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The oxide layer is deposited on the finFET before the metal strap is formed. This preliminary action creates an electrical isolation barrier in advance, preventing electrical shorting and parasitic coupling from the beginning of the manufacturing process, while maintaining simplicity in subsequent manufacturing steps.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8860112B2finFET eDRAM strap connection structure
Publication Date: 2014.10.14 GLOBALFOUNDRIES US INC
  • US8860112B2 patent drawing
  • US8860112B2 patent drawing
  • US8860112B2 patent drawing

AI summary

A method of forming a strap connection structure for connecting an embedded dynamic random access memory (eDRAM) to a transistor comprises forming a buried oxide layer in a substrate, the buried oxide layer defining an SOI layer on a surface of the substrate; forming a deep trench through the SOI layer and the buried oxide layer in the substrate; forming a storage capacitor in a lower portion of the deep trench; conformally doping a sidewall of an upper portion of the deep trench; depositing a metal strap on the conformally doped sidewall and on the storage capacitor; forming at least one fin in the SOI layer, the fin being in communication with the metal strap; forming a spacer over the metal strap and over a juncture of the fin and the metal strap; and depositing a passive word line on the spacer.