FinFETs with Different Fin Profiles for Areal Density and Gate Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in further shrinking the size and increasing the speed of field-effect transistors (FETs) while maintaining effective gate control, as existing technologies struggle to optimize both area density and performance in integrated circuits.
Innovation Solution
The integration of FinFETs with different fin profiles, including non-tiered and tiered fins, on a single substrate, allows for the formation of both high-density and speed-critical circuits, such as SRAM cells and logic devices, by optimizing fin profiles and well configurations to enhance gate control and areal density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If FinFETs are shrunk to increase areal density, then area density is improved, but gate control of the channel deteriorates
Solution Approach 1:
The patent transitions from planar 2D FET channels to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change allows the gate to wrap around the channel in a triple-gate configuration, providing superior electrostatic control while maintaining small footprint area, thus resolving the contradiction between areal density and gate control
Solution Approach 2:
The gate structure is nested around the vertical fin channel, with the gate electrode wrapping around three sides of the fin. This nested configuration maximizes gate control over the channel while minimizing the device area, enabling both high areal density and effective gate control simultaneously
2Speed
If FinFETs are shrunk to increase speed, then device speed is improved, but gate control of the channel deteriorates
Solution Approach 1:
By moving to vertical FinFET structures, the gate achieves wraparound control of the channel, providing strong electrostatic control that enables faster switching speeds even as device dimensions are reduced. The three-dimensional gate configuration maintains control effectiveness at smaller scales, supporting higher speed operation
Solution Approach 2:
The FinFET structure uses asymmetric geometry with vertical fins and wrapped gates that provide enhanced control at critical dimensions. The unequal distribution of gate material around the channel (covering three sides rather than one) creates asymmetric field distribution that improves control and enables faster switching
3Reliability
If different fin profiles are used to optimize specific circuits, then device performance is improved, but device complexity increases
Solution Approach 1:
The patent applies different fin profile characteristics to different regions or device types within the integrated circuit. By tailoring fin dimensions, angles, and profiles locally to specific circuit requirements (e.g., different profiles for logic vs. memory devices), optimal performance is achieved for each function while maintaining a manageable overall device architecture
Data Source
AI summary
An integrated circuit is provided. The integrated circuit includes a substrate, a first FinFET device supported by the substrate, the first FinFET device having a first fin with a non-tiered fin profile, and a second FinFET supported by the substrate, the second FinFET having a second fin with a tiered fin profile.