FinFET Gate Isolation via Dummy Gate Trench Insulation
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating finFET transistors with reduced short channel effects and improved isolation between gates, particularly in achieving precise control over the formation of semiconductor fins and insulating structures to enhance device performance and density.
Innovation Solution
The method involves forming semiconductor fins on a substrate using photolithography and epitaxial growth, followed by the creation of gate insulator layers, dummy layers, and insulating structures, with a trench formation and replacement gate process to achieve precise control over gate dimensions and isolation, allowing for efficient deposition of insulating materials and reduction of critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used to form fins and gates, then manufacturing process is simpler, but isolation between gates is insufficient and short channel effects increase
Solution Approach 1:
The patent applies preliminary action by forming insulating structures between fins before forming the gates. This sequence ensures proper isolation is established early in the fabrication process, preventing short channel effects and improving gate isolation without requiring complex post-processing steps.
Solution Approach 2:
The fabrication process is segmented into distinct sequential steps: first forming insulating structures between fins, then forming gates. This segmentation allows each structure to be optimized independently, ensuring proper isolation while maintaining manufacturing feasibility.
2Productivity
If fin dimensions are reduced to increase device density, then device density increases, but short channel effects worsen
Solution Approach 1:
By forming insulating structures between fins before gate formation, the patent establishes proper electrical isolation that suppresses short channel effects even when fin dimensions are reduced to increase device density.
Solution Approach 2:
The patent introduces localized insulating structures between adjacent fins, providing targeted electrical isolation where needed most. This local quality enhancement allows fin dimensions to be reduced for higher density while maintaining reliable short channel effect control through the insulating barriers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of finFET transistors with improved isolation and reduced short channel effects, enhancing device performance and density by allowing for precise control over gate and insulating structure formation, thereby addressing the challenges of existing fabrication methods.
Implementation Method 1
forming semiconductor fins on a substrate using photolithography and epitaxial growth
Implementation Method 2
forming semiconductor fins on a substrate using photolithography and epitaxial growth
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a shallow trench isolation (STI) structure surrounding a pair of semiconductor fins; forming a dummy gate layer over the STI structure and the semiconductor fins; etching a first portion of the dummy gate layer to form a trench through the dummy gate layer until the STI structure is exposed, in which the trench extends between the semiconductor fins along a lengthwise direction of the semiconductor fins; forming an insulating structure in the trench through the dummy gate layer; after forming the insulating structure extending through the dummy gate layer, patterning the dummy gate layer to form a pair of dummy gate structures each of which is across a respective one of the semiconductor fins; and replacing the dummy gate structures with a pair of metal gate structures.