Fin-Type FET Gate Width Design via Variable Height Segmentation
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Solution Overview
Problem
Conventional fin-type FET manufacturing methods are limited in gate width design due to a fixed height of the semiconductor layer, making it difficult to apply these transistors to existing circuits or design circuits with varying device dimensions.
Innovation Solution
A semiconductor device manufacturing method that forms first and second projecting regions with different heights, allowing for the formation of gate insulating films and gate electrodes on both upper and side faces, and diffusion regions underneath, enabling adjustable gate width design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the height of the semiconductor layer projecting in a fin-shape is fixed to achieve a simple manufacturing process, then the manufacturing precision is improved, but the adaptability of device design is worsened because the gate width cannot be changed
Solution Approach 1:
The semiconductor layer is divided into multiple regions with different heights (first projecting region with first height, second projecting region with second height). This segmentation allows each region to have different gate widths while maintaining consistent manufacturing processes, resolving the contradiction between manufacturing precision and design adaptability.
Solution Approach 2:
Different regions of the semiconductor layer are given different local properties (different heights) to achieve different gate widths. The first projecting region has a first height for one gate width, while the second projecting region has a second height for another gate width, enabling design flexibility without compromising manufacturing precision.
2Reliability
If the semiconductor layer thickness is reduced to achieve thorough depletion during operation, then the transistor performance is improved, but the gate width design flexibility is worsened due to the fixed fin height
Solution Approach 1:
The semiconductor layer is segmented into multiple projecting regions with different heights, allowing each region to be optimized for thorough depletion while maintaining different gate width designs. This enables both high reliability through effective depletion and design flexibility for various device dimensions.
Solution Approach 2:
The height parameter of the semiconductor layer is varied across different regions (first height vs. second height) to achieve different gate widths. This parameter change allows each region to be optimized for thorough depletion while providing flexibility in device dimension design.
3Ease of manufacture
If a single fin height is used to simplify the manufacturing process, then the ease of manufacture is improved, but the ability to design circuits with various device dimensions is worsened
Solution Approach 1:
The manufacturing process is segmented into stages where a uniform semiconductor layer is first formed (maintaining ease of manufacture), then selectively etched to create multiple projecting regions with different heights (enabling circuit design flexibility). This segmentation allows both simple manufacturing and versatile design.
Solution Approach 2:
A uniform semiconductor layer with consistent thickness is formed in advance before selective etching. This preliminary action maintains ease of manufacture, while subsequent selective removal of portions creates different fin heights for various gate widths, enabling circuit design flexibility.
Data Source
AI summary
Including a process for forming a fin 12a having a first height and a fin 12b having a second height lower than the first height, a process for forming a silicon oxide film on the upper and side faces of each of the fins 12a and 12b, a process for forming a conductive poly silicon film on the silicon oxide film, a process for forming a gate insulating film 15 and a gate electrode 16 on from the upper face to the side face of each of the fins 12a and 12b by patterning the silicon oxide film and the poly silicon film, and a process for forming a couple of diffusion regions 14 in two regions clipping a region underneath the gate electrode of each of the fins 12a and 12b. According to the present invention, a semiconductor device manufacturing method and a semiconductor device including a fin-type FET having capability of changing the design of the gate width corresponding to an application can be realized.