FinFET Isolation Gap Fill Using Flowable Deposition and Annealing
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Solution Overview
Problem
As semiconductor devices shrink, the short channel leakage effect becomes significant, leading to inadequate gate control over the channel region, especially in conventional planar transistors, resulting in increased leakage current, which FinFETs aim to mitigate through a unique gate structure and isolation region formation.
Innovation Solution
The formation of FinFETs with a gate structure that wraps around the active region and the use of flowable chemical vapor deposition (FCVD) to fill gaps between fins with a dielectric material, followed by annealing and chemical mechanical polish processes to create effective intra-device and inter-device isolation regions, enhancing gate control and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are used with reduced minimum feature size to increase integration density, then more components can be integrated into a given area, but leakage current increases due to short channel leakage effect
Solution Approach 1:
The patent transitions from conventional planar transistors to FinFETs by introducing a three-dimensional fin structure that protrudes from the substrate. This dimensional change allows the gate to wrap around the channel region on three sides, providing superior electrostatic control and reducing short channel leakage effects while maintaining scaled dimensions for high integration density
2Productivity
If the gate length is reduced to scale devices into deep sub-30 nanometer dimensions, then integration density improves, but the gate cannot fully control the channel region leading to increased leakage
Solution Approach 1:
By forming vertical fins that protrude from the substrate, the patent creates a three-dimensional structure where the gate wraps around the channel region. This dimensional transformation provides enhanced gate control over the channel even at deep sub-30 nanometer dimensions, preventing short channel leakage while maintaining high integration density
3Reliability
If dielectric material is deposited to fill gaps between fins, then isolation regions are formed to improve gate control, but excess dielectric material must be removed requiring additional processing steps
Solution Approach 1:
The patent employs flowable chemical vapor deposition (FCVD) to deposit dielectric material with controlled flow properties that enable gap filling. The deposited dielectric material undergoes annealing to densify it, and subsequent selective removal processes precisely shape the isolation regions. These parameter changes in deposition and processing enable effective gate control while managing process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage current by improving gate control over the channel region, allowing for better on/off switching characteristics in FinFETs, even at deep sub-30 nanometer dimensions, thereby addressing the short channel leakage issue.
Implementation Method 1
filling the gaps between the fins with a dielectric material through a flowable chemical vapor deposition (FCVD) process
Implementation Method 2
performing an annealing process to reduce leakage current
Implementation Method 3
performing a chemical mechanical polish process to remove excess portions of the dielectric material above the fins
Data Source
AI summary
An isolation region gap fill method comprises depositing a first dielectric material over a semiconductor device through a flowable deposition process or other gap fill deposition processes, wherein the semiconductor device includes a first FinFET comprising a plurality of first fins and a second FinFET comprising a plurality of second fins. The method further comprises removing the first dielectric material between the first FinFET and the second FinFET to form an inter-device gap, depositing a second dielectric material into the inter-device gap and applying an annealing process to the semiconductor device.