FinFET Layout Effect Mitigation via Intact Interlayer Dielectric
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Solution Overview
Problem
Conventional FinFET fabrication processes using long isolation cut masks introduce stresses and increase deviation from the desired threshold voltage due to etching of the interlayer dielectric, leading to undesirable layout effects.
Innovation Solution
Maintaining the interlayer dielectric (ILD) layer intact at the junction between the gate cut and isolation cut masks during fabrication, using perpendicular masks to avoid merging of isolation cuts and reduce strain accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If long isolation cut masks are used in conventional FinFET fabrication, then the isolation cuts can be performed, but stresses are introduced and threshold voltage deviation increases due to etching of the interlayer dielectric
Solution Approach 1:
The patent segments the long isolation cut mask into multiple shorter isolation cut masks that are positioned at different locations. This segmentation prevents the need for a single long mask that would require etching through the interlayer dielectric, thereby reducing stress introduction while still achieving complete isolation. Each shorter mask can be processed independently without compromising the interlayer dielectric integrity.
Solution Approach 2:
The patent introduces a new dimensional approach by adding a second set of isolation cuts oriented perpendicular to the first set. Instead of relying solely on long isolation cuts in one direction, the perpendicular isolation cuts create a grid-like isolation pattern that achieves the same isolation effect with shorter individual cut lengths, preventing interlayer dielectric etching.
2Reliability
If the gate cut and isolation cut are separated by design, then fabrication integrity can be maintained, but lithography process limitations cause the isolation cuts to merge
Solution Approach 1:
The patent employs asymmetric positioning of the segmented isolation cut masks relative to the gate cut. Rather than symmetric placement that would require larger spacing, the isolation cuts are strategically positioned at asymmetric locations where they can be closer to the gate cut without risking merge, optimizing use of the available lithography process window.
Solution Approach 2:
The patent performs preliminary positioning of multiple shorter isolation cut masks before the actual isolation cut process. By pre-positioning these segmented masks at optimized locations, the process ensures that even with lithography variations, the isolation cuts remain separated and do not merge with the gate cut or each other.
3Reliability
If isolation cut length is increased to ensure coverage, then isolation effectiveness improves, but threshold voltage deviation from target increases
Solution Approach 1:
The patent divides the isolation function into multiple shorter segments rather than using a single long isolation cut. This segmentation maintains isolation effectiveness by ensuring complete separation at each segment location while keeping individual cut lengths short enough to avoid etching through the interlayer dielectric and introducing stress that would cause threshold voltage deviation.
Solution Approach 2:
The patent applies isolation cuts with different local characteristics - multiple shorter cuts positioned at specific locations rather than one long continuous cut. Each local isolation cut is optimized to provide sufficient isolation at its specific position without the cumulative stress effect of a long continuous cut, thereby maintaining threshold voltage accuracy while achieving effective isolation.
Data Source
Figure 1A~1D
Figure 2A~2C
Figure 3A~3C
AI summary
Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.