FinFET MOL Process Using Self-Aligned Trench-Silicide for 7.5 nm Tracks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in fabricating high-density finFET devices lies in achieving precise control over the spacing and routing of metal lines at the 10 nm node, particularly in creating standard cell library devices, where lithographic limitations and the short channel effect hinder efficient use of semiconductor wafer area and lead to issues in processing at 7.5 nm track spaces.
Innovation Solution
A six-mask middle of line (MOL) process is developed, enabling a 10 nm architecture with 31.5 nm fin pitch in a 7.5 nm track design, using self-aligned gate borderless Trench-Silicide (TS) and local interconnect structures, which eliminates the need for V0 via and allows M0 to land directly on the contact block (CB), utilizing LELE processing for precise metal line formation and patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length of FETs is decreased to improve switching speed and increase device density, then the operating speed and FET density are improved, but the short channel effect worsens, making it difficult to control the electrical potential of the channel
Solution Approach 1:
The patent transitions from planar FET structures to FinFET structures, utilizing vertical fins to create a three-dimensional channel. This dimensional change allows the gate to control the channel from multiple sides (trigate or dual-gate configuration), providing superior electrostatic control over the channel potential even at reduced channel lengths, thereby mitigating the short channel effect while maintaining high switching speed.
2Power
If multiple fins are used in parallel to increase current flow and drive strength, then the drive strength is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges multiple fin structures into a unified FinFET device where multiple fins are formed in parallel within a single device footprint. The gate structure envelops multiple fins simultaneously, creating a combined current path that delivers high drive strength. This merging approach achieves the equivalent of multiple parallel FETs while reducing overall device complexity and simplifying manufacturing processes.
3Productivity
If lithographic processes are used to form metal lines at 7.5 nm track spaces, then the metal line formation is achieved, but the manufacturing precision and spacing control become difficult due to lithographic limitations
Solution Approach 1:
The patent employs self-aligned processes where sacrificial mandrels are formed first, followed by deposition of metal lines that automatically align to the mandrel positions. This preliminary action of creating alignment references before metal deposition ensures precise spacing control at 7.5 nm track pitches, overcoming lithographic resolution limitations through self-alignment mechanisms that eliminate the need for high-precision lithographic patterning of the metal lines themselves.
4Adaptability or versatility
If standard cell library devices are created with cross coupling, then the functionality is improved, but the use of semiconductor wafer area becomes inefficient
Solution Approach 1:
The patent designs FinFET-based standard cell library devices where the FinFET structure serves multiple functions: the vertical fins provide high drive strength, the tri-gate or dual-gate configuration enables effective channel control, and the compact footprint allows efficient packing. Cross-coupled devices share common structures and interconnects, allowing a single physical implementation to fulfill multiple logical functions, thereby improving wafer area utilization while maintaining full functionality.
Data Source
AI summary
At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.