Fin-Shaped FET Doping Uniformity and Corner Integrity
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Solution Overview
Problem
Conventional methods for producing fin-shaped FETs fail to achieve desirable transistor characteristics due to uneven impurity region doping, leading to higher sheet resistance in side portions compared to upper portions, and excessive chipping of fin-shaped semiconductor region corners during plasma doping.
Innovation Solution
The method involves setting the pressure during plasma doping to be less than or equal to 0.6 Pa to reduce ion density and control the implantation dose, ensuring the side portion impurity region's sheet resistance is equal to or greater than 80% of the upper portion's, and using a plasma doping process that maintains a low ion current density to minimize corner etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional plasma doping is used to form impurity regions in fin-shaped semiconductor regions, then doping is achieved, but the sheet resistance in side portions becomes higher than in upper portions and corner chipping occurs
Solution Approach 1:
The patent applies parameter changes by carefully controlling plasma doping conditions including ion energy (5-50 eV), ion flux, and doping atmosphere composition to achieve uniform impurity concentration in both upper and side portions of fin-shaped semiconductor regions, preventing corner chipping while maintaining desirable transistor characteristics
Solution Approach 2:
The patent implements local quality by creating uniformly doped impurity regions that specifically address the side portions of fin-shaped semiconductor regions, ensuring that the doping characteristics are optimized for the three-dimensional fin structure rather than applying uniform doping across all surfaces
2Productivity
If ion density is increased during plasma doping to improve doping efficiency, then doping rate increases, but corner chipping of fin-shaped semiconductor regions worsens
Solution Approach 1:
The patent resolves this contradiction by optimizing ion energy to a specific range of 5-50 eV and controlling ion flux during plasma doping, achieving efficient doping while preventing corner chipping through precise parameter control rather than simply increasing ion density
Solution Approach 2:
The patent applies dynamics by dynamically controlling plasma parameters including ion energy and ion flux during the doping process, adjusting conditions to maintain both high doping efficiency and corner integrity throughout the doping cycle
3Reliability
If sheet resistance of side portion impurity region is reduced to improve transistor characteristics, then doping concentration increases, but corner chipping during plasma doping increases
Solution Approach 1:
The patent achieves low sheet resistance without corner chipping by changing plasma doping parameters to control ion energy (5-50 eV) and ion flux, enabling high doping concentration in side portions while maintaining corner integrity through optimized process conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves transistor characteristics by equalizing the sheet resistance of impurity regions and reducing corner chipping, resulting in enhanced drain current and productivity while maintaining high conformal doping properties.
Implementation Method 1
a plasma doping method is employed to implant an impurity into a fin-shaped semiconductor region
Implementation Method 2
implanting an impurity into a fin-shaped semiconductor region by a plasma doping method
Data Source
AI summary
A semiconductor device includes: a first semiconductor region formed on a substrate and having an upper surface and a side surface; a first impurity region of a first conductivity type formed in an upper portion of the first semiconductor region; a second impurity region of a first conductivity type formed in a side portion of the first semiconductor region; and a gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first semiconductor region. A radius of curvature r′ of an upper corner of a portion of the first semiconductor region located outside the gate insulating film is greater than a radius of curvature r of an upper corner of a portion of the first semiconductor region located under the gate insulating film and is less than or equal to 2r.