FinFET PTSL Formation via Dummy Gate Ion Reflection
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Solution Overview
Problem
Existing FinFET manufacturing processes face increased leakage current and short channel effects due to non-uniform doping concentration in the Punch-Through-Stop Layer (PTSL) at the edges of fins, especially as gate lengths decrease below 20 nm.
Innovation Solution
A method involving ion implantation to form the PTSL directly under the gate, with reflection doped layers on the inner sides of source/drain regions, reducing junction leakage and capacitance, and improving threshold voltage by forming the PTSL without doped regions beneath the source/drain regions, and using spacers to reflect ions and create doped regions on opposite sides of the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If ion implantation is used to form PTSL in the fin after fin and isolation layer formation, then leakage current between source and drain regions is reduced, but non-uniform doping concentration at fin edges increases leakage current and short channel effects
Solution Approach 1:
A dummy gate structure is introduced as an intermediary element during the ion implantation process. The dummy gate acts as a mask that prevents ions from reaching the fin edges, ensuring uniform doping concentration in the PTSL. After implantation, the dummy gate is removed and replaced with the actual gate, achieving both leakage reduction and doping uniformity.
Solution Approach 2:
The dummy gate is formed before the ion implantation step to pre-establish the desired doping pattern. This preliminary structure guides the ion implantation process to achieve uniform PTSL doping concentration, preventing edge effects before they occur.
2Productivity
If gate length is continuously decreased to increase integration, then device density increases, but short channel effects become more significant and leakage current increases
Solution Approach 1:
The PTSL is formed with uniform doping concentration specifically in the channel region under the gate, while reflection doped regions are created at the source/drain interfaces. This localized quality control addresses short channel effects at critical locations without compromising the overall device scaling and integration density.
Solution Approach 2:
The ion reflection that would normally cause non-uniform doping at fin edges is converted into a beneficial effect. The reflected ions create reflection doped regions at the source/drain interfaces, which improve threshold voltage control and reduce leakage current, turning a manufacturing defect into a performance enhancement.
3Object-affected harmful factors
If PTSL is formed with doped regions beneath source and drain regions, then leakage current is reduced, but junction capacitance increases and threshold voltage control deteriorates
Solution Approach 1:
The dummy gate serves as an intermediary mask during ion implantation, preventing ions from forming doped regions directly beneath the source and drain regions. This selective blocking reduces junction capacitance while the reflection doped regions at the interfaces maintain leakage current suppression.
Solution Approach 2:
Doping is localized to specific regions: uniform PTSL under the gate channel and reflection doped regions at source/drain interfaces. This local quality control avoids forming doped regions beneath source/drain regions, reducing junction capacitance while maintaining leakage reduction through the PTSL and interface doped regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces junction leakage and capacitance, prevents threshold voltage roll-off, and enhances short channel effects by ensuring the PTSL is only under the gate and forming reflection doped regions that improve the device's performance as it scales down.
Implementation Method 1
implanting ions to form a Punch-Through-Stop Layer (PTSL) in a portion of the fin directly under the opening
Implementation Method 2
due to presence of a spacer of the dummy device, ions close to the spacer are reflected and implanted into portions of the fin on inner sides of the source/drain regions beneath the spacer
Data Source
AI summary
There is provided a method of manufacturing a Fin Field Effect Transistor (FinFET). The method may include: forming a fin on a semiconductor substrate; forming a dummy device including a dummy gate on the fin; forming an interlayer dielectric layer to cover regions except for the dummy gate; removing the dummy gate to form an opening; implanting ions to form a Punch-Through-Stop Layer (PTSL) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions; and forming a replacement gate in the opening.