FinFET Sidewall Gate Structure for Nonvolatile Memory Integration
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Solution Overview
Problem
High integration density in semiconductor devices leads to short channel effects, degrading the characteristics of field effect transistors, particularly in nonvolatile memory devices like flash memories and DRAMs, causing defects and reducing productivity due to high step differences in processing steps.
Innovation Solution
A semiconductor device and method featuring fins on a substrate with opposing sidewalls, where first and second gate lines act as spacers, and impurity layers form a channel region between them, with charge-trapping insulation films and bit lines connected in parallel, allowing for a floating channel region used as a data storage field, minimizing short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel length is shortened to increase integration density, then the number of unit elements increases, but short channel effects deepen and transistor characteristics deteriorate
Solution Approach 1:
The patent introduces a vertical FinFET structure where the channel is formed on the sidewalls of a fin rather than a planar surface. This three-dimensional configuration increases the effective channel area without increasing the planar footprint, thereby improving integration density while maintaining transistor characteristics through better gate control in the vertical dimension
Solution Approach 2:
The channel region is segmented into multiple sidewall channels formed on opposite sides of the fin structure. This segmentation allows each sidewall channel to be independently controlled by gate lines, improving overall device performance and enabling higher integration through compact arrangement of multiple channels in a small area
2Reliability
If storage node heights are increased to improve capacitor performance, then data storage capability increases, but step differences increase causing processing defects
Solution Approach 1:
The patent employs a nested structure where bit lines are formed within openings that penetrate through insulating layers, and storage nodes are positioned within the fin structure. This nesting allows compact vertical arrangement of components, achieving high capacitor performance while minimizing surface step differences that would otherwise cause processing defects
Solution Approach 2:
The invention transitions from planar capacitor design to a vertical three-dimensional structure where storage nodes are formed on fin sidewalls and bit lines access them through vertical openings. This dimensional change enables improved capacitor performance within a smaller footprint and reduces step differences on the chip surface
Data Source
AI summary
Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed in the pattern of spacer on the second sidewall of the fin. First and second impurity regions are disposed in the fin. The first and second impurity regions are isolated from each other and define a channel region in the fin between the first and second gate lines.