FinFET Gate Structure Using Silicon Nitride Protective Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing FinFET devices face issues such as silicon consumption during high temperature anneal and etching processes, leading to poor critical dimension uniformity, fin damage, and leakage due to thermal stress, as well as non-conformity and thinness of the gate oxide layer.
Innovation Solution
A silicon nitride based layer is formed conformally over a lining oxide layer on the semiconductor fin, preventing silicon consumption, enhancing structural strength, and ensuring uniformity and conformity of the gate oxide layer, thereby maintaining critical dimensions and preventing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high temperature anneal and etching processes are performed on semiconductor fins, then isolation structures are formed and fins are recessed, but silicon consumption occurs leading to poor critical dimension uniformity
Solution Approach 1:
A silicon nitride based layer is formed conformally over the semiconductor fin before the high temperature anneal and etching processes. This preliminary protective layer prevents silicon consumption during subsequent processing, maintaining critical dimension uniformity while allowing isolation structures to be formed and fins to be recessed.
Solution Approach 2:
The silicon nitride based layer acts as an intermediary protective barrier between the semiconductor fin and the high temperature anneal/etching processes. It mediates the interaction by preventing direct silicon consumption while still allowing the necessary processing to occur, thus preserving critical dimension uniformity.
2Ease of manufacture
If high temperature anneal processes are performed, then isolation structures are formed, but thermal stress damages the semiconductor fin
Solution Approach 1:
The silicon nitride based layer is formed conformally over the semiconductor fin before the high temperature anneal process. This preliminary protective coating shields the fin from thermal stress damage while allowing the isolation structures to be formed through the anneal process.
Solution Approach 2:
The silicon nitride based layer serves as a protective intermediary between the semiconductor fin and the thermal stress of high temperature annealing. It absorbs or distributes the thermal stress, preventing direct damage to the fin structure while enabling isolation structure formation.
3Ease of manufacture
If gate oxide layer is formed directly on semiconductor fin, then gate dielectric is provided, but the layer is non-conformal and thin leading to leakage
Solution Approach 1:
The silicon nitride based layer is formed conformally over the semiconductor fin before the gate oxide layer formation. This preliminary conformal layer provides a uniform foundation that ensures the gate oxide layer achieves good conformity and appropriate thickness, preventing leakage while maintaining ease of manufacture.
Solution Approach 2:
The silicon nitride based layer acts as an intermediary foundation between the semiconductor fin and the gate oxide layer. It provides a conformal surface that mediates the gate oxide formation process, ensuring uniform thickness and good conformity while preventing direct contact issues between the gate oxide and fin.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution maintains critical dimension uniformity, prevents fin damage, and ensures good gate oxide layer conformity, enhancing the performance and yield of FinFET devices by resisting thermal stress and maintaining fin integrity during high temperature processes.
Implementation Method 1
A silicon nitride based layer is formed conformally over a lining oxide layer on the semiconductor fin
Implementation Method 2
enhancing the performance and yield of FinFET devices by resisting thermal stress and maintaining fin integrity during high temperature processes
Data Source
AI summary
A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.