FinFET 6T SRAM Cell Read Write Margin Optimization
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Solution Overview
Problem
Conventional FinFET 6T SRAM devices have poor read noise margin and write margin due to small β and γ ratios, which result in incomplete charge transfer and slow data switching.
Innovation Solution
A static memory circuit with a pull-up transistor, a pull-down transistor, and a pass-gate transistor, where the ratio of Fins in each transistor is optimized to achieve a β ratio greater than or equal to 1.2 for read operations and a γ ratio greater than or equal to 1.5 for write operations, improving the noise margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FinFET 6T SRAM devices use standard Fin ratios, then device complexity is reduced, but read noise margin and write margin deteriorate due to small β and γ ratios
Solution Approach 1:
The patent applies parameter changes by optimizing the Fin ratios of different transistors (PU, PD, PG) to achieve specific β ratio (≥1.2) and γ ratio (≥1.5) values. This involves changing the physical dimensions and configuration parameters of the FinFET structures to improve read noise margin and write margin while maintaining device functionality.
2Reliability
If the number of Fins in PD and PG transistors is increased to improve β ratio, then read noise margin improves, but device area increases
Solution Approach 1:
The patent applies local quality by differentiating the Fin configurations across different transistor types within the same memory cell. Specifically, PD transistors are designed with 2 Fins and PG transistors with 3 Fins, while PU transistors maintain 1 Fin. This localized optimization allows achieving β≥1.2 and improved read noise margin without uniformly increasing the area of all transistors.
3Reliability
If the Fin ratio of PG to PU transistors is increased to improve γ ratio, then write margin improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by establishing specific target values for γ ratio (≥1.5) and configuring PG transistors with 3 Fins versus PU transistors with 1 Fin. These defined parameter targets provide clear manufacturing specifications that balance the need for improved write margin with achievable fabrication precision requirements.
Data Source
AI summary
A static memory circuit includes a pull-up transistor, a pull-down transistor, a pass-gate transistor associated with the pull-up and pull-down transistors, and first and second word lines electrically insulated from each other. The pass-gate transistor includes a number of Fins and a gate electrode having a number of first and second gates, each one of the gates is disposed on one of the Fins, the first gates are connected to the first word line, and the second gates are connected to the second word line. During a read operation, one of the first and second word lines is asserted low, so that the beta ratio is greater than or equal to a first predetermined value. During a write operation, one of the first and second word lines is asserted high; so that a gamma ratio is greater than or equal to a second predetermined value.