FinFET Non-Recessed STI Trench Segmentation for Epitaxial Uniformity
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Solution Overview
Problem
Fin field effect transistors (FinFETs) face irregular epitaxial body formation at the edge of fins due to incomplete coverage by spacer material, affecting device performance, particularly in NMOS and PMOS devices using silicon germanium (SiGe) and silicon carbide (SiC), which introduce channel stress and contact resistance issues.
Innovation Solution
A method involving a non-recessed shallow-trench isolation (STI) process is implemented, where a dummy gate structure is formed on the semiconductor fin, and a trench is created to divide the fin into portions, allowing for uniform epitaxial growth by forming initial gate structures and electrodes on both sides, ensuring complete coverage and regular recess shapes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single dummy gate is formed on STI to reduce design circuit surface area, then area is reduced, but spacer material does not completely cover the edge of fins, resulting in irregular epitaxial body and affecting device performance
Solution Approach 1:
The fin is divided into two separate portions by forming a trench between them. This segmentation allows each portion to have its own complete spacer material coverage and independent epitaxial body formation, eliminating the irregularity problem that occurs at the edge of a single fin when using a single dummy gate configuration.
2Reliability
If SiGe and SiC are used in PMOS and NMOS devices to introduce channel stress and reduce contact resistance, then contact resistance is reduced, but irregular epitaxial body formation at fin edges affects device performance
Solution Approach 1:
By segmenting the fin into two portions with a trench between them, each portion can accommodate SiGe or SiC epitaxial growth independently with complete spacer coverage, ensuring uniform epitaxial body formation while maintaining the low contact resistance benefits of SiGe/SiC materials.
3Device complexity
If a non-recessed STI process with single dummy gate is used, then manufacturing complexity is reduced, but incomplete spacer coverage causes irregular epitaxial problems
Solution Approach 1:
The fin segmentation approach maintains the simplicity of the non-recessed STI process and single dummy gate configuration while solving the epitaxial irregularity problem. The trench division allows complete spacer coverage on each fin portion, achieving regular epitaxial bodies without increasing overall process complexity.
Data Source
AI summary
A method of manufacturing a semiconductor device includes providing a semiconductor structure having a substrate and a semiconductor fin on the substrate, forming a dummy gate structure on the semiconductor fin, forming a first dielectric layer on the semiconductor structure exposing an upper surface of the dummy gate structure, removing the dummy gate structure and a portion of the semiconductor fin below the dummy gate structure to form a trench that divides the semiconductor fin into a first portion and a second portion spaced apart from each other, and forming a second dielectric layer on the semiconductor structure filling the trench. The method provides a semiconductor device having a non-recessed trench isolation structure.