FinFET Gate Structures with Tapered Profiles for Uniform Etching
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Solution Overview
Problem
The semiconductor industry faces challenges in forming gate structures for FinFETs due to a loading effect during the etching of dummy gate layers, which results in uneven trench depths and profiles, affecting device performance, particularly in small and large gate pitch regions.
Innovation Solution
The formation of an etch barrier with varying thicknesses, achieved through plasma treatment or wet processes, allows for isotropic etching of the dummy gate layer, resulting in tapered profiles that mitigate the loading effect and enable more uniform trench formation across different pitch regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for dummy gate layers, then the etching process is simple and fast, but uneven trench depths and profiles are produced due to loading effects, worsening manufacturing precision
Solution Approach 1:
An etch barrier layer is formed on the dummy gate structure before the main etching process. This preliminary barrier layer is designed to compensate for the loading effect by having varying thickness that pre-corrects for the uneven etching rates that will occur during subsequent etching, thereby achieving uniform trench depths without requiring complex real-time process control
Solution Approach 2:
The etch barrier layer thickness is varied as a function of position along the dummy gate structure. By changing the barrier layer thickness parameter across different regions, the process compensates for the loading effect and achieves uniform etching results across the entire structure
2Reliability
If dummy gate layers are etched without compensation, then the process is simple, but leakage current increases due to uneven profiles affecting device performance
Solution Approach 1:
The etch barrier layer is formed in advance to pre-compensate for loading effects, ensuring that the final trench profiles are uniform and device performance is optimized, thereby reducing leakage current while maintaining manufacturing simplicity
Solution Approach 2:
The etch barrier layer acts as an intermediary element between the dummy gate structure and the etching process. It mediates the etching interaction by providing a controlled resistance to etching that compensates for loading effects, thereby protecting device performance and reducing leakage current
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage current in FinFETs by ensuring consistent profiles of the replacement gate structures, improving device performance and efficiency across various technology nodes, including 16 nm and smaller.
Implementation Method 1
The formation of an etch barrier with varying thicknesses, achieved through plasma treatment or wet processes
Implementation Method 2
The formation of an etch barrier with varying thicknesses, achieved through plasma treatment or wet processes
Implementation Method 3
allows for isotropic etching of the dummy gate layer, resulting in tapered profiles
Data Source
AI summary
Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths.