FinFET Threshold Voltage Control via Chloride Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of Field-Effect Transistors (FinFETs) faces challenges in accurately controlling and uniformity of source and drain region undercuts, which affect performance due to the pattern loading effect caused by fin pattern density, making it difficult to maintain consistent threshold voltages across FinFETs on the same chip.
Innovation Solution
The method involves forming gate stacks on semiconductor fins, performing tilted n-type doping to create uniform impurity profiles, and using chlorine radicals for precise etching to form recesses, allowing for epitaxial growth of source and drain regions, thereby controlling the gate proximity and threshold voltage of FinFETs with high accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form recesses, then the etching process can be completed, but the undercut profiles vary significantly due to pattern loading effects
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial layer and performing selective epitaxial growth before the final etching step. The sacrificial layer is deposited and patterned in advance, and epitaxial regions are grown selectively in recesses based on this pre-formed pattern. This preliminary structuring enables precise control of subsequent etching operations, ensuring uniform undercut profiles despite variations in pattern density across the chip.
2Adaptability or versatility
If the pattern density of exposed fin portions varies, then different regions of the chip are formed, but the undercuts vary significantly due to pattern loading effect
Solution Approach 1:
The patent implements local quality by creating spatially varying structures through selective epitaxial growth. The sacrificial layer and epitaxial regions are formed with local variations in composition and structure that correspond to the underlying fin pattern density. This local differentiation enables each region to be processed according to its specific pattern density requirements, achieving uniform undercuts across the entire chip despite global variations in fin spacing.
3Manufacturing precision
If accurate undercut control is required, then the etching process must be precisely controlled, but this becomes difficult due to pattern loading effects
Solution Approach 1:
The patent introduces an intermediary sacrificial layer and epitaxial structure that mediates between the fin pattern and the final recess formation. This intermediary layer absorbs the variability introduced by pattern loading effects, providing a stable reference structure that simplifies the subsequent etching process. The intermediary structures act as a buffer that decouples the sensitivity of undercut control from the variability of the underlying fin pattern.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of FinFET profiles and threshold voltages, minimizing process variations and pattern loading effects, resulting in consistent performance across FinFETs with adjustable threshold voltages and reduced STI and gate loss.
Implementation Method 1
The first and the second n-type doped regions are etched using chlorine radicals to form a first recess and a second recess, respectively
Implementation Method 2
An epitaxy is performed to re-grow a first semiconductor region and a second semiconductor region in the first recess and the second recess, respectively
Implementation Method 3
performing implantations to implant exposed portions of the first and the second semiconductor fins to form a first and a second n-type doped region
Data Source
AI summary
A method includes forming a first and a second gate stack to cover a first and a second middle portion of a first and a second semiconductor fin, respectively, and performing implantations to implant exposed portions of the first and the second semiconductor fins to form a first and a second n-type doped region, respectively. A portion of each of the first and the second middle portions is protected from the implantations. The first n-type doped region and the second n-type doped region have different gate proximities from edges of the first gate stack and the second stack, respectively. The first and the second n-type doped regions are etched using chlorine radicals to form a first and a second recess, respectively. An epitaxy is performed to re-grow a first semiconductor region and a second semiconductor region in the first recess and the second recess, respectively.