FinFET Vertical Dimension Tuning via Selective Ion Implantation
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Solution Overview
Problem
FinFET devices have limitations in achieving multiple vertical dimensions for fins on the same semiconductor wafer, requiring complex processing steps and increased silicon surface area, which hinders the design of dense high-performance CMOS circuits with varying on-current requirements.
Innovation Solution
A method to form finFET devices with multiple vertical dimensions using a simple and inexpensive process, involving implantation of an species into semiconductor fins to create alloys at the bottom portion, followed by selective etching and dielectric deposition, allowing for different fin heights while maintaining identical top surfaces, enabling the design of dense high-performance CMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If thermal oxidation process is used to reduce fin height, then multiple vertical dimensions can be achieved, but the process becomes complex and increases manufacturing steps
Solution Approach 1:
The patent applies preliminary action by forming a mask layer and patterned hard mask before the thermal oxidation process. This pre-preparation of masking structures enables the selective reduction of fin heights through subsequent oxidation, achieving multiple vertical dimensions without requiring complex in-situ control during the oxidation process itself.
Solution Approach 2:
The patent uses mask layers and patterned hard masks as intermediary structures to mediate the thermal oxidation process. These intermediary masking layers enable selective oxidation of specific fin regions, creating different vertical dimensions without directly controlling the oxidation process itself, thus simplifying the overall manufacturing complexity.
2Adaptability or versatility
If multiple fins are used to achieve different on-currents, then current requirements can be met, but silicon surface area increases and device design becomes less area-efficient
Solution Approach 1:
The patent transitions from controlling on-current through horizontal dimension (number of fins) to controlling it through vertical dimension (fin height). By varying the vertical height of fins while maintaining the same footprint area, the patent achieves different on-currents without increasing silicon surface area, thus improving area efficiency.
Solution Approach 2:
The patent applies local quality by creating fins with different vertical dimensions within the same device structure. Specific fins are selectively reduced in height to achieve desired current ratios (e.g., beta ratio in SRAM cells) while other fins maintain full height, enabling precise on-current control without expanding the overall device area.
3Ease of manufacture
If fin height is fixed for all finFETs, then manufacturing is simplified, but the ability to achieve different on-currents is limited
Solution Approach 1:
The patent maintains ease of manufacture by using a uniform fin formation process for all fins initially, then applies selective local modification through mask layers and patterned hard masks. This allows most fins to maintain the standard height for simplified manufacturing, while specific fins are selectively reduced to achieve required on-current variations for different circuit functions.
Solution Approach 2:
The patent segments the fin structure into different vertical zones using mask layers and patterned hard masks. This segmentation allows different portions of fins to be at different heights (full height vs. reduced height), enabling multiple on-current values from a single uniform manufacturing process while maintaining ease of manufacture for the majority of structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the creation of finFET devices with multiple vertical dimensions using a minimal number of additional processing steps, allowing for the design of dense high-performance CMOS devices with varied on-currents, such as in SRAM cells, by adjusting the depth of implantation to tune the beta ratio effectively.
Implementation Method 1
implantation of an species into the bottom portion of the semiconductor fins to form an alloy
Implementation Method 2
a patterned photoresist masks selected ones of the semiconductor fins from the ion implantation
Data Source
AI summary
A semiconductor structure and its method of fabrication include multiple finFETs with different vertical dimensions for the semiconductor fins. An implant species is implanted in a bottom portion of selected semiconductor fins on which reduced vertical dimension is desired. The bottom portion of the selected semiconductor fins with implant species is etched selective to the semiconductor material without the implanted species, i.e., the semiconductor material in the top portion of the semiconductor fin and other semiconductor fins without the implanted species. FinFETs with the full vertical dimension fins and a high on-current and finFETs with reduced vertical dimension fins with a low on-current thus results on the same semiconductor substrate. By adjusting the depth of the implant species, the vertical dimension of the semiconductor fins may be adjusted in selected finFETs.