FIR Coefficient Scaling to Reduce Quantization Noise Overflow
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Solution Overview
Problem
Conventional FIR filters face significant computation errors due to quantization noise and large filter coefficients, which cannot be adequately reduced by existing techniques, leading to deterioration in filter characteristics.
Innovation Solution
A filter device comprising delay units, multiplication units, a coefficient adjustment unit, a signal conversion unit, and a division unit, where filter coefficients are adjusted by multiplying design values with a factor and dividing by a maximum representation value to minimize computation errors, and signals are processed to reduce errors associated with multiplication and addition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If filter coefficients are adjusted by multiplying with a large multiplying factor to reduce quantization noise, then quantization noise is reduced, but the multiplication result exceeds the maximum representation range causing overflow
Solution Approach 1:
The patent divides the filter coefficient adjustment process into two separate stages: first multiplying the design value by the multiplying factor to get an intermediate result, then dividing by the maximum representation range value. This segmentation allows the multiplication to use a larger factor for noise reduction while the subsequent division brings the result back within the representable range, preventing overflow.
Solution Approach 2:
The patent introduces an intermediate value (the multiplication result before division) that temporarily exceeds the maximum representation range. This intermediate value serves as a mediator that allows the use of a larger multiplying factor for better precision, while the final division operation ensures the stored coefficient remains within valid bounds.
2Loss of substance
If the range in which filter coefficients are represented is kept small to maintain low quantization bit rates, then transmission and storage efficiency is improved, but the multiplying factor for error correction cannot be sufficiently large
Solution Approach 1:
The patent extends the computation space by allowing intermediate multiplication results to exceed the maximum representation range. This dimensional extension in the computation domain enables the use of larger multiplying factors for better error correction, while the final result is folded back into the original representation range through division, maintaining low bit rates for storage and transmission.
3Ease of manufacture
If filter coefficients are rounded to fit within the representation range, then storage and transmission are simplified, but computation error increases
Solution Approach 1:
The patent performs preliminary multiplication of the design value by the multiplying factor before rounding or truncation to fit the representation range. This preliminary action with an enlarged scale allows for better precision in the intermediate result, and the subsequent division by the maximum representation range value ensures the final stored coefficient is within valid bounds while retaining improved precision.
Data Source
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AI summary
A filter device (100) includes: a plurality of delay units (1-1 to 1-N) connected in series to give a delay to an input signal and output a delayed signal; a plurality of multiplication units (2-0 to 2-N) that multiply the delayed signal by a filter coefficient generated based on a predetermined value and a multiplying factor adjustment value; a coefficient adjustment unit (3) that, when a multiplication result obtained by multiplying the predetermined value by the multiplying factor adjustment value exceeds a maximum value of a representation range of the filter coefficient, divides the multiplication result exceeding the maximum value by the maximum value, and outputs a quotient of the division as a coefficient adjustment value; a signal conversion unit (4) that outputs a signal obtained by adding after-filter-coefficient-multiplication signals outputted by the multiplication units and an adjusted signal obtained by adjusting a corresponding delayed signal using the coefficient adjustment value; and a division unit (5) that generates an output signal by dividing the signal outputted by the signal conversion unit by the multiplying factor adjustment value.