FIR Input DAC Parallel Taps for Pop- and Click-Free Gain Control

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Solution Overview

Problem

Existing digital-to-analog converters for personal audio devices do not support multi-level signal filtering and require binary signal processing, leading to inefficiencies and signal artifacts like 'pops' and 'clicks'.

Innovation Solution

A digital-to-analog converter with an integrator and input network featuring parallel taps of varying signal delays, controlled by selective enabling and disabling to achieve desired analog gain and filter characteristics, minimizing signal artifacts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a serial string of resistors is used for analog gain control, then the input resistance can be programmed, but no filtering of the digital input signal occurs and signal artifacts like pops and clicks appear

Engineering Contradiction:
Improveinput resistance programmingVSAvoidsignal artifacts
Core Design Contradiction:
Ease of operationVSObject-generated harmful factors

Solution Approach 1:

The patent divides the single gain control function into multiple parallel tap paths, each with its own delay element and gain control. This segmentation allows independent control of gain and filtering characteristics without interfering with each other, eliminating signal artifacts while maintaining programming capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces delay elements as intermediary components between the digital input signal and the gain control stage. These delay elements act as mediators that smooth out the binary signal transitions, preventing direct coupling of switching artifacts to the output while still allowing gain programming through the parallel tap structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If binary signal processing is used, then the digital-to-analog converter can operate with simple circuitry, but multi-level signal filtering is not supported

Engineering Contradiction:
Improveconverter circuitryVSAvoidmulti-level signal filtering
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent adds the time dimension by introducing delay elements to the traditional binary DAC structure. By processing signals at multiple time delays through parallel paths, the system achieves multi-level filtering capability while maintaining the simplicity of binary input processing. This transforms a one-dimensional binary switching problem into a multi-dimensional time-sampled signal processing solution.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides controlled analog gain and effective filtering, reducing signal artifacts and enhancing waveform matching, while maintaining low harmonic distortion and crosstalk noise.

Implementation Method 1

an integrator, an input network

Methodology Applied
Scientific EffectIntegration:

Data Source

PatentUS12574045B2Finite impulse response input digital-to-analog converter
Publication Date: 2026.03.10 CIRRUS LOGIC INC
  • US12574045B2 patent drawing
  • US12574045B2 patent drawing
  • US12574045B2 patent drawing

AI summary

A digital-to-analog converter (DAC) may include an integrator, an input network, and control circuitry. The input network may include a plurality of parallel taps, each having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member is coupled between an input of the digital-to-analog converter and an input of the integrator. The control circuitry may be configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the DAC, such that the control circuitry enables, substantially contemporaneously, an even number of members at a time in order to increase the analog gain, with half of such enabled members in a first group and half of such enabled members in a second group.