FIR Input DAC Tap Network for Multi-Level PWM Filtering

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Solution Overview

Problem

Existing digital-to-analog converters for personal audio devices, such as wireless telephones and media players, face challenges in converting digital PWM signals to analog signals without filtering, which limits their ability to support multi-level signals and results in errors.

Innovation Solution

A digital-to-analog converter with an integrator and an input network of parallel taps, each with a respective input resistance, where control circuitry selectively enables and disables taps to program the effective input resistance and control analog gain, allowing for filtering and reducing errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a traditional PWM signal conversion approach with serial resistors is used, then the circuit structure is simple, but filtering cannot be performed and multi-level signals are not supported

Engineering Contradiction:
Improvemulti-level signal supportVSAvoidcircuit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The input network is segmented into multiple parallel taps, each with its own switch and resistor. This segmentation allows the circuit to selectively activate different taps to create multi-level output signals while maintaining a relatively simple overall structure. Each tap represents a discrete level, enabling filtering capabilities without requiring a complex multi-stage circuit.

Inventive Principle:
Principle #1Segmentation

2Reliability

If traditional PWM conversion without filtering is used, then the circuit is simple, but signal artifacts like pops and clicks occur

Engineering Contradiction:
Improvesignal qualityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The filtering action is performed preliminarily through the parallel tap structure before the signal reaches the integrator. By pre-establishing multiple discrete levels through the selective activation of parallel taps, the circuit prepares a filtered-like signal that reduces artifacts before further processing, thereby improving signal quality without adding complex post-processing stages.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If parallel taps with different signal delays are used, then filtering and multi-level signals are supported, but the control circuitry complexity increases

Engineering Contradiction:
Improvefiltering capabilityVSAvoidcontrol circuitry
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The control circuitry operates periodically by enabling and disabling specific parallel taps in a systematic sequence. This periodic control pattern allows the circuit to cycle through different tap combinations to achieve filtering effects and multi-level signals. The periodic nature of the control simplifies the logic requirements compared to arbitrary complex control sequences, as it follows a predictable repeating pattern.

Inventive Principle:
Principle #19Periodic action

4Reliability

If an even number of parallel taps are enabled at a time, then signal artifacts are minimized, but the gain control range is constrained

Engineering Contradiction:
Improveartifact reductionVSAvoidgain control range
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The circuit compensates for the even-tap constraint by dynamically changing other parameters, specifically by adjusting the resistance values in the feedback network and modifying the integrator characteristics. This allows the system to achieve a wide effective gain control range despite the limitation of enabling only an even number of parallel taps at any given time, thereby maintaining artifact reduction while preserving gain versatility.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12009829B2Finite impulse response input digital-to-analog converter
Publication Date: 2024.06.11 CIRRUS LOGIC INC
  • US12009829B2 patent drawing
  • US12009829B2 patent drawing
  • US12009829B2 patent drawing

AI summary

A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member of the plurality of parallel taps is coupled between an input of the digital-to-analog converter and an input of the integrator, and control circuitry configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter, such that the control circuitry enables an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.