FIR Decimation Filter Using Shared MACs and Coefficient Memory
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Solution Overview
Problem
Existing decimation filters for communication systems require significant hardware complexity and large pipeline delay registers to achieve high rejection of out-of-band signals, particularly in poly-phase filter implementations.
Innovation Solution
A Finite Impulse Response (FIR) filter design with a reduced hardware complexity, utilizing a small number of multiply-and-accumulate (MAC) units connected in parallel, and a coefficient memory accessed by a counter and multiplexer, which allows for efficient decimation without the need for extensive pipeline delay registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a poly-phase filter is used to achieve high rejection of out-of-band signals, then filter performance is improved, but hardware complexity increases due to large pipeline delay registers and multiple MAC units
Solution Approach 1:
The filter is divided into multiple polyphase components (e.g., 4 components for decimation factor 64), each processed by a separate MAC unit in parallel. This segmentation allows the system to achieve high rejection performance while reducing the burden on individual processing units and eliminating the need for large pipeline delay registers.
Solution Approach 2:
The filter operates by periodically selecting one output from the multiple MAC units based on the decimation factor. A multiplexer selects outputs at periodic intervals (e.g., every 64th sample), enabling high-rate decimation with reduced hardware complexity by not requiring all MAC unit outputs to be continuously processed.
2Productivity
If multiple MAC units are used to parallelize poly-phase filter operations, then processing speed is improved, but hardware complexity increases
Solution Approach 1:
Multiple MAC units are merged into a single integrated structure that shares common resources such as coefficient memory and control logic. The MAC units operate in parallel but are coordinated through a unified control mechanism, achieving high processing speed while reducing overall hardware complexity compared to fully independent MAC unit implementations.
Solution Approach 2:
The MAC units are designed to be multi-functional, where each unit can process different polyphase components and coefficients. This universality allows the same hardware structure to be reused across multiple processing paths, reducing the total number of dedicated components needed and lowering hardware complexity while maintaining high processing throughput.
3Measurement precision
If a conventional poly-phase filter implementation is used, then high rejection of out-of-band signals is achieved, but the use of large pipeline delay registers increases hardware resources
Solution Approach 1:
The large pipeline delay registers traditionally required in poly-phase filters are extracted and replaced by a more efficient memory structure. Coefficients are stored in a compact memory array that is accessed directly by the MAC units, eliminating the need for extensive pipeline delay registers while maintaining the filter's ability to achieve high rejection of out-of-band signals.
Solution Approach 2:
Instead of using large pipeline delay registers to store and shift sample values through multiple stages, the system uses a memory-based approach where coefficients are copied and distributed to multiple MAC units. This copying mechanism allows parallel processing of polyphase components without requiring the physical delay line infrastructure, significantly reducing hardware resource consumption.
Data Source
AI summary
A Finite Impulse Response (FIR) filter that reduces the complexity of the hardware required for a filter with a high decimation factor while achieving similar performance of prior art poly-phase filters of greater complexity. The FIR filter includes a small number of multiply-and-accumulate (MAC) units connected in parallel to each other between an input stream and an output stream. The MAC units are provided with coefficients from a memory. In an example implementation, the memory is addressed by a counter and the output of the memory selected by a multiplexer for suppling the coefficients.