FIR Filter Circuit Input Rearrangement for Lower Power
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Solution Overview
Problem
Conventional delay tap finite impulse response (FIR) filters face significant power consumption issues due to continuous triggering and data transfer between registers, especially when the number of taps is large, leading to inefficient signal processing.
Innovation Solution
A low-power filter circuit design incorporating a switch circuit that rearranges input data or coefficients based on a count value, eliminating the need for continuous data transfer among registers by using a modulo operation to adjust the arrangement of inputs or coefficients, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous triggering is used to process input signals in a filter circuit, then signal processing functionality is maintained, but power consumption increases significantly
Solution Approach 1:
The patent implements periodic action by using a counter to track the number of input signals and only triggering the filter circuit when the counter reaches a predetermined threshold value. This converts continuous triggering into periodic triggering, maintaining signal processing functionality while significantly reducing power consumption by keeping the circuit in a low-power state between triggering events.
2Reliability
If the number of taps in the filter is increased to improve filtering performance, then filter capability is enhanced, but power consumption increases due to more register transfers
Solution Approach 1:
The patent applies periodic action by accumulating input signals in registers and only performing filter computation when a predetermined number of signals are collected. This allows the filter to handle large numbers of taps without continuous power consumption, as the register transfers and computational operations occur periodically rather than continuously for each input signal.
Solution Approach 2:
The patent implements preliminary action by pre-storing multiple input signals in registers before triggering the filter computation. This accumulation phase prepares the data in advance, so that when the threshold is reached, the filter can process all accumulated signals efficiently in one triggering event, reducing the overall frequency of power-intensive operations.
3Productivity
If data is continuously transferred between registers to maintain filter operation, then signal processing is continuous, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by continuously storing incoming input signals in registers during an accumulation phase without triggering computation. This preliminary data collection occurs in a low-power state, and only when the predetermined number of signals is accumulated does the circuit trigger the power-intensive filter computation, thus maintaining continuous signal processing capability while reducing overall power consumption.
Data Source
AI summary
A filter circuit includes multiple registers, a switch circuit, multiple multipliers and a summation circuit. Each register is configured to store an input. The switch circuit is coupled to the registers and configured to receive the inputs from the registers as a series of registered inputs and adjust arrangement of the inputs of the series of registered inputs to generate a series of rearranged inputs according to a count value. The count value is accumulated in response to reception of a new input of the filter circuit. The multipliers are coupled to the switch circuit. The inputs of the series of rearranged inputs are sequentially provided to the multipliers. Each multiplier is configured to generate a multiplication result according to the received input and a coefficient. The summation circuit is coupled to the multipliers and configured to sum up the multiplication results to generate an output.