Low Power FIR Filter Multi-MAC Architecture Scheduling
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Solution Overview
Problem
Digital signal processors (DSP) architectures face challenges in achieving high performance while minimizing power dissipation, particularly in portable electronics where low power consumption is essential.
Innovation Solution
A multi-MAC architecture is implemented, where multiple multiply-accumulate units are scheduled to operate in parallel, using a single coefficient value for multiple cycles and shifting output results between units to reduce power dissipation and optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple MAC units are used simultaneously to maximize performance, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by scheduling MAC units to operate in alternating cycles rather than continuously. Each MAC unit performs computations for a predetermined number of cycles, then enters a low-power state while other units take over, creating a periodic operation pattern that reduces overall power consumption while maintaining throughput performance
Solution Approach 2:
The system dynamically allocates workloads between multiple MAC units based on computational requirements. The scheduling mechanism dynamically activates or deactivates specific MAC units depending on the current processing needs, allowing the system to adapt power consumption levels to actual performance requirements rather than operating all units at constant capacity
2Productivity
If multiple MAC units operate in parallel, then productivity is improved, but power dissipation increases
Solution Approach 1:
The patent segments the computational workload across multiple MAC units with dedicated coefficient sets. Each MAC unit is responsible for specific portions of the FIR filter computations, allowing the system to divide and conquer the processing task while only activating the necessary segments (MAC units) for each processing cycle, thereby reducing overall power dissipation
Solution Approach 2:
The system discards the active state of MAC units when they are not currently needed for processing, allowing them to enter low-power modes. The scheduling mechanism recovers computational capacity by activating different MAC units in different cycles, effectively discarding and recovering power consumption states to match actual processing demands
Data Source
AI summary
Embodiments of the invention are directed to system and method that enable relatively low power dissipation by scheduling operations of multiply accumulators chain of two or more multiply accumulators units by delivering an output result of a first multiply accumulator of the chain as an input to a second subsequent multiply accumulator of the chain.