Complex Multiplier-Accumulator Unit for FIR Filter Convolution
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Solution Overview
Problem
Digital signal processors face inefficiencies in performing convolution operations for finite impulse response filters due to underutilization of multipliers, especially when dealing with complex and real number inputs and coefficients, leading to higher power consumption and lower throughput.
Innovation Solution
A digital signal processor with a complex multiplier-accumulator unit that includes four multipliers to perform parallel multiplications of complex and real numbers, allowing for efficient calculation of convolutions by directing inputs and coefficients through multiplexers based on their nature, enabling simultaneous execution of multiple multiplications in different computation modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a digital signal processor uses a conventional multiplier-accumulator unit with limited parallel multiplication capability, then the device complexity is reduced, but the productivity and power efficiency deteriorate due to underutilization of multipliers when processing complex and real number convolutions
Solution Approach 1:
The patent implements a dynamic multiplier-accumulator unit that can adapt its operation mode based on the input data types. The control circuitry dynamically configures the multiplier bank to perform different numbers of parallel multiplications depending on whether the inputs are complex or real numbers, optimizing resource utilization for each specific computation scenario without requiring separate dedicated hardware for each mode
Solution Approach 2:
The patent designs a universal multiplier-accumulator unit that can handle multiple computation modes (complex-by-complex, complex-by-real, real-by-real) using the same hardware resources. The same bank of multipliers can be configured to perform different types of multiplications based on control signals, eliminating the need for separate dedicated multiplier sets for each operation type
2Productivity
If a digital signal processor performs sequential multiplications instead of parallel multiplications, then the device complexity is reduced, but the loss of time and productivity deteriorate
Solution Approach 1:
The patent segments the convolution computation into multiple parallel multiplication operations that can be executed simultaneously. The control circuitry divides the input sequences into groups and directs them to different multipliers in parallel, breaking down the sequential process into concurrent segments that complete faster when executed simultaneously
Solution Approach 2:
The control circuitry performs preliminary configuration of the multiplier-accumulator unit by pre-loading input sequences into registers and pre-configuring the multiplier bank based on the data types before execution. This preliminary setup enables the multipliers to immediately begin parallel operations without sequential configuration delays during the actual computation phase
3Use of energy by moving object
If a digital signal processor uses dedicated multipliers for each multiplication operation, then the productivity is improved, but the use of energy increases due to underutilization of hardware resources
Solution Approach 1:
The patent changes the operational parameters of the multiplier-accumulator unit based on the input data types. When processing complex-by-real convolutions, the control circuitry adjusts the configuration to enable exactly two parallel multiplications per clock cycle, matching the computational requirements precisely. This parameter adaptation ensures that the hardware resources are fully utilized without excess, optimizing the energy-to-throughput ratio
Data Source
AI summary
A processor for calculating a convolution of a first input sequence of numbers with a second input sequence of numbers to generate an output sequence is provided. The processor includes multipliers, each multiplying two real numbers to generate an output; multiplexers to direct the numbers in the first and second input sequences or parts of the numbers to the multipliers; and control circuitry to control the multiplexers to direct the first and second input sequences of numbers to the multipliers dependent on whether the numbers are complex or real. An accumulator adds partial products from multiplications performed by the multipliers to calculate the convolution.