Differential Current Mode FIR Filter for Noise Reduction
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Solution Overview
Problem
Semi-analog FIR filters face challenges in implementing a chain of Sample and Hold Amplifiers due to gain errors and noise, leading to corrupted samples, and existing multipliers are limited by uni-polar current sources and accuracy issues.
Innovation Solution
The implementation of a differential current mode device with a weighted addition deferred after multiplication, using a partially segmented DAC and selectively enabling duplicate devices to enhance signal-to-noise ratio and reduce current consumption, while operating with non-radix2 and utilizing two resistor networks for complex filter operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a chain of Sample and Hold Amplifiers is implemented in semi-analog FIR filters, then the filter can process signals through multiple taps, but gain errors and noise accumulate leading to corrupted samples
Solution Approach 1:
The filter is divided into multiple independent taps, each with its own multiplier and DAC. Instead of chaining Sample and Hold Amplifiers, each tap processes the input signal independently from the input buffer, then all tap outputs are summed. This segmentation isolates error sources and prevents noise accumulation across stages.
Solution Approach 2:
A buffer amplifier is introduced as an intermediary between the input signal source and each tap's multiplier. This buffer provides high input impedance to prevent loading effects and drives the multiple tap inputs with consistent signal levels, isolating the signal source from the complex tap network.
2Ease of manufacture
If traditional multipliers with uni-polar current sources are used, then the circuit implementation is straightforward, but accuracy is limited due to current source constraints
Solution Approach 1:
Instead of using uni-polar current sources that limit the multiplier's dynamic range, the invention employs differential current mode operation where currents can flow in both directions. This inversion of the current source approach allows the multiplier to handle both positive and negative signal values with high precision, overcoming the fundamental limitation of traditional uni-polar implementations.
3Measurement precision
If full precision DACs are used at each tap, then coefficient accuracy is maintained, but current consumption increases and signal-to-noise ratio deteriorates
Solution Approach 1:
The invention uses a reduced-precision DAC at each tap position, providing only the most significant bits of the coefficient. The remaining less significant bits are reconstructed through digital signal processing in the output stage. This partial action approach reduces DAC current consumption and noise while maintaining overall filter precision through the combination of reduced-precision DAC outputs and digital refinement.
4Measurement precision
If all DAC segments are always enabled, then full coefficient resolution is available, but current consumption increases and signal-to-noise ratio decreases
Solution Approach 1:
The DAC segments are dynamically enabled or disabled based on the current coefficient value being implemented. Control logic monitors the coefficient magnitude and activates only the necessary DAC segments required to represent that coefficient with sufficient precision. This dynamic adaptation reduces unnecessary current consumption and minimizes noise from inactive DAC segments while maintaining full coefficient resolution when needed.
Data Source
AI summary
Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non-radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein. Another circuit implements a multiplying element and digital-to-analog converter with selective enablement of duplicate current source devices. Another circuit implements a multiplying element and digital-to-analog converter with variable effective length of the digital-to-analog converter. In one such circuit one or more current sources of a multiplier element are deselected to remove a noise contribution of the multiplier element, as described herein. A complex filter circuit includes a pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a common resistor network to perform weighted addition. One such circuit further includes a second pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a second common resistor network to perform weighted addition.